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MT9V124EBKSTC-CR Datasheet(PDF) 7 Page - ON Semiconductor

Part # MT9V124EBKSTC-CR
Description  Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9V124EBKSTC-CR Datasheet(HTML) 7 Page - ON Semiconductor

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MT9V124_DS Rev.C Pub. 5/15 EN
7
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Sensor Core
The MT9V124 has a color image sensor with a Bayer color filter arrangement and a VGA
active-pixel array with electronic rolling shutter (ERS). The sensor core readout is 10 bits.
The sensor core also supports separate analog and digital gain for all four color channels
(R, Gr, Gb, B).
Image Flow Processor (IFP)
The advanced IFP features and flexible programmability of the MT9V124 can enhance
and optimize the image sensor performance. Built-in optimization algorithms enable
the MT9V124 to operate with factory settings as a fully automatic and highly adaptable
system-on-a-chip (SOC) for most camera systems.
These algorithms include shading correction, defect correction, color interpolation,
edge detection, color correction, aperture correction, and image formatting with crop-
ping and scaling.
Microcontroller Unit (MCU)
The MCU communicates with all functional blocks by way of an internal ON Semicon-
ductor proprietary bus interface. The MCU firmware executes the automatic control
algorithms for exposure and white balance.
System Control
The MT9V124 has a phase-locked loop (PLL) oscillator that can generate the internal
sensor clock from the common system clock. The PLL adjusts the incoming clock
frequency up, allowing the MT9V124 to run at almost any desired resolution and frame
rate within the sensor’s capabilities.
Low-power consumption is a very important requirement for all components of medical
devices. The MT9V124 provides power-conserving features, including an internal soft
standby mode and a hard standby mode.
A two-wire serial interface bus enables read and write access to the MT9V124’s internal
registers and variables. The internal registers control the sensor core, the color pipeline
flow, the output interface, auto white balance (AWB) and auto exposure (AE).
Output Interface
Image data is provided to the host system by a serial LVDS interface. The Start bit, 8-bit
image data, Line_Valid, Frame_Valid and Stop bit are packetized in a 12-bit packet. The
output data format is available in either raw data or processed data. Processed data
format includes YCbCr, RGB-565, BT656 with odd SAV/EAV code. It also supports the
SOC Bypass 8+2 data format over the 12-bit packet.
System Interfaces
Figure 2 on page 8 shows typical MT9V124 device connections. For low-noise operation,
the MT9V124 requires separate power supplies for analog and digital sections. Both
power supply rails should be decoupled from ground using capacitors as close as
possible to the die.
The MT9V124 provides dedicated signals for digital core and I/O power domains that
can be at different voltages. The PLL and analog circuitry require clean power sources.
Table 3, “Pin Descriptions,” on page 9 provides the signal descriptions for the MT9V124.


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