MT9V125IA7XTC-DR datasheet(8/68 Pages) ONSEMI

Part #	MT9V125IA7XTC-DR

Description	PAL CMOS Digital Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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MT9V125_DS Rev.. W 6/15 EN

8

©Semiconductor Components Industries, LLC,2015.

MT9V125: SOC VGA Digital Image Sensor

Typical Connections

Figure 3 shows a detailed MT9V125 device configuration. For low-noise operation, the

MT9V125 requires separate analog and digital power supplies. Incoming digital and

analog ground conductors can be tied together next to the die.

Power supply voltages VAA (the primary analog voltage) and VAAPIX (the main voltage to

the pixel array) should be decoupled from ground with an LC filter. The MT9V125

requires a single external voltage supply level.

Figure 3:

Typical Configuration Without Use of Overlay

Notes:

1. MT9V125 STANDBY can be connected directly to the customer’s ASIC controller or to DGND, depend-

ing on the controller’s capability.

2. A 1.5K resistor value is recommended, but may be greater for slower two-wire speed (for exam-

ple, 100 KB/sec).

3. LVDS_ENABLE must be tied HIGH if LVDS is to be used.

4. Pull down DAC_REF with a 2.8K resistor for 1.0V peak-to-peak video output.

5. VAA and VAAPIX must be tied to the same potential for proper operation.

6. Low pass filter (3dB attenuation at 4.2 MHz).

AGND

0.1µF

VAA

DGND

1µF

VDD

VAAPIX

1µF

AGND

0.1µF

1µF

VDD

Power

VAA

Power

SDATA

SCLK

RESET_BAR

LVDS_ENABLE3

FRAME_VALID

PIXCLK

LINE_VALID

DOUT[7:0]

EXTCLK

SADDR

STANDBY1

DGND

AGND

DGND

AGND

VDD

VAA

VAAPIX

Two-Wire

Serial Interface

Master Clock

STANDBY from

Controller

or Digital GND

PEDESTAL

NTSC_PAL_SELECT

HORIZ_FLIP

DAC_NEG

DAC_POS

LVDS_NEG

LVDS_POS

DAC_REF

DIN[7:0]

DIN_CLK

DOUT_LSB[1:0]

RSVD

75

Ω Terminated Receiver

VDDDAC

Power

VDDPLL

Power

VDDDAC

VDDPLL

8

2

Low Pass Filter6

VAAPIX5

Power

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MT9V125IA7XTC-DR Datasheet(PDF) 8 Page - ON Semiconductor

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