© Semiconductor Components Industries, LLC, 2010

December, 2010 − Rev. 0

1

Publication Order Number:

NB7VQ14M/D

NB7VQ14M

1.8V/2.5V/3.3V 8GHz /

14Gbps Differential 1:4

Clock / Data CML Fanout

Equalizer

Multi−Level Inputs w/ Internal Termination

Description

The NB7VQ14M is a high performance differential 1:4 CML fanout

buffer with a selectable Equalizer receiver. When placed in series with

a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the

NB7VQ14M inputs will compensate the degraded signal transmitted

across a FR4 PCB backplane or cable interconnect and output four

identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V

power supply. Therefore, the serial data rate is increased by reducing

Inter−Symbol Interference (ISI) caused by losses in copper

interconnect or long cables. The EQualizer ENable pin (EQEN)

allows the IN/IN inputs to either flow through or bypass the Equalizer

section. Control of the Equalizer function is realized by setting EQEN;

When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When

EQEN is set High, the IN/IN inputs flow through the Equalizer. The

default state at start−up is LOW. As such, NB7VQ14M is ideal for

SONET, GigE, Fiber Channel, Backplane and other Clock/Data

distribution applications.

The differential inputs incorporate internal 50

W termination

resistors that are accessed through the VT pin. This feature allows the

NB7VQ14M to accept various logic level standards, such as LVPECL,

CML or LVDS. The 1:4 fanout design was optimized for low output

skew applications.

The NB7VQ14M is a member of the GigaComm

™ family of high

performance clock products.

Features

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

QFN−16

MN SUFFIX

CASE 485G

16

NB7V

Q14M

ALYWG

G

1

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

1

EQ

SIMPLIFIED BLOCK DIAGRAM