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TPS65270 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS65270 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 27 page COMP1 COMP EA CS SLP 0.8V ILIM Latch S R Q Q EN OSC Internal LDO BUCK 1 BUCK 2 Pre-Regulator, Voltage Reference, Current Bias 23 21,22 24 19, 20 14 15,16 17,18 13 6 8 3 2 4 1 10 11 9 12 5 Logic VIN1 BST1 LX1 FB1 VIN1 VOUT BUCK1 GND BST2 LX2 FB2 VOUT BUCK2 GND VIN2 FB1 SS1 FB1 FB2 COMP2 SS2 FB2 LOW_P VCC ROSC EN 1 Logic EN1 EN2 Logic EN2 AGND 6 same as Buck 1 VIN2 180 o Note: Pin numbers in block diagram are for HTSSOP (PWP) 24-pin package. TPS65270 www.ti.com SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013 FUNCTIONAL BLOCK DIAGRAM ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING PWP (R-PDSO-G) TPS65270PWPR TPS65270 –40°C to 85°C RGE (S-PVQFN-N24) TPS65270RGER or TPS65270RGET TPS65270 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS65270 |
Similar Part No. - TPS65270_15 |
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Similar Description - TPS65270_15 |
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