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TPS65400-Q1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS65400-Q1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 75 page  TPS65400-Q1 SLVSCQ2 – JULY 2015 www.ti.com Pin Functions PIN DESCRIPTION NAME NO. CB1 1 Bootstrap pin for high-side MOSFET gate drive for SW1 2 SW1 3 Switch pin for SW1 4 PVIN1 5 Power input for buck switching regulator SW1 PVIN2 6 Power input for SW2 PGND1 7 Power ground for buck converters PGND2 8 Power ground for buck converters 9 SW2 10 Switch pin for SW2 11 CB2 12 Bootstrap pin for SW2 high-side MOSFET gate drive ENSW2 13 Enable input pin for SW2. Active high. 2-µA internal pullup current is inside. VFB2 14 Feedback input pin for SW2 Compensation pin for external compensation network for SW2. Pulling this line high to VDDD configures the COMP2 15 SW1 controller to control both SW1 and SW2. Soft-start for SW2 (default). A capacitor is used to set the startup time. This pin can also be reconfigured SS2/PG2 16 through I2C to display the PGOOD2 signal instead. Default PGOOD signal is for all switchers. It can be changed according to (D2h) PIN_CONFIG_00. If all PGOOD 17 switchers are disabled, PGOOD is low. VDDG 18 Supply for gate drives. Bypass locally to PGND. VDDA 19 Output of internal regulator for analog controls. VDDD 20 3.3-V output of internal regulator digital controls AGND 21 Ground connection for analog controls VIN 22 Analog VIN. Power input pin for VDDD, VDDA, and VGATE subregulator power Chip enables. Internal pull-up current will default to high if the pin is left floating. Connect to an open-drain output to pull low to disable. Driving with a push-pull output is not recommended. When low, internal regulators are CE 23 shutdown to minimize power, and functionsa are disabled. Configuration is reloaded from EEPROM as part of the power-up sequence when CE goes high. Soft-start for SW3 (default). A capacitor is used to set the startup time. This pin can also be reconfigured SS3/PG3 24 through I2C to display the PGOOD3 signal instead. COMP3 25 Compensation pin for external compensation network for SW3 VFB3 26 Feedback input pin for SW3 ENSW3 27 Enable input pin for SW3. Active high. 2-µA internal pullup current is inside. CB3 28 Bootstrap pin for SW3 high-side MOSFET gate drive SW3 29 Switch pin for SW3. Max rated output current is 2 A. PVIN3 30 Power input for buck switching regulator SW3 PVIN4 31 Power input for SW4 SW4 32 Switch pin for SW4. Max rated output current is 2 A. CB4 33 Bootstrap pin for SW4 high-side MOSFET gate drive ENSW4 34 Enable input pin for SW4. Active high. 2-µA internal pullup current is inside. VFB4 35 Feedback input pin for SW4 Compensation pin for external compensation network for SW4. Pulling this line high to VDDD configures the COMP4 36 SW3 controller to control both SW3 and SW4. Soft-start for SW4 (default). A capacitor is used to set the startup time. This pin can also be reconfigured SS4/PG4 37 through I2C to display the PGOOD4 signal instead I2CADDR 38 Select I2C address with resistor to AGND Reset of digital logic. When low, all switchers are disabled. Configuration is reloaded from EEPROM when RST_N 39 RESET_N is deasserted. RCLOCK_SYNC 40 Resistor for setting master clock frequency from 275 kHz to 2.2 MHz or for clock sync 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65400-Q1 |
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