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CAV25256VE-GT3 Datasheet(PDF) 1 Page - ON Semiconductor |
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CAV25256VE-GT3 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 13 page © Semiconductor Components Industries, LLC, 2013 June, 2013 − Rev. 0 1 Publication Order Number: CAV25256/D CAV25256 256-Kb SPI Serial CMOS EEPROM Description The CAV25256 is a 256−Kb Serial CMOS EEPROM device internally organized as 32Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25256 device. The device features software and hardware write protection, including partial as well as full array protection. On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications. Features • Automotive Temperature Grade 1 (−40°C to +125°C) • 10 MHz (5 V) SPI Compatible • 2.5 V to 5.5 V Supply Voltage Range • SPI Modes (0,0) & (1,1) • 64−byte Page Write Buffer • Additional Identification Page with Permanent Write Protection • Self−timed Write Cycle • Hardware and Software Protection • Block Write Protection − Protect 1/4, 1/2 or Entire EEPROM Array • Low Power CMOS Technology • 1,000,000 Program/Erase Cycles • 100 Year Data Retention • 8−lead SOIC and TSSOP Packages • This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant SI SO CAV25256 SCK VSS VCC CS WP HOLD Figure 1. Functional Symbol http://onsemi.com PIN CONFIGURATIONS SI HOLD VCC VSS WP SO CS 1 See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ORDERING INFORMATION SOIC−8 V SUFFIX CASE 751BD SCK SOIC (V), TSSOP (Y) TSSOP−8 Y SUFFIX CASE 948AL Chip Select CS Serial Data Output SO Write Protect WP Ground VSS Serial Data Input SI Serial Clock SCK Function Pin Name PIN FUNCTION Hold Transmission Input HOLD Power Supply VCC (Top View) |
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