KAF-4301 Image Sensor

www.truesenseimaging.com

Revision 2.1 PS-0038Pg9

Pin

Name

Description

Pin

Name

Description

1

φV2

Vertical (Parallel) CCD Clock - Phase 2

40

φV2

Vertical (Parallel) CCD Clock - Phase 2

2

φV2

Vertical (Parallel) CCD Clock - Phase 2

39

φV2

Vertical (Parallel) CCD Clock - Phase 2

3

φV1

Vertical (Parallel) CCD Clock - Phase 1

38

φV1

Vertical (Parallel) CCD Clock - Phase 1

4

φV1

Vertical (Parallel) CCD Clock - Phase 1

37

φV1

Vertical (Parallel) CCD Clock - Phase 1

5

VSUB

Substrate

36

VSUB

Substrate

6

N/C

No Connection

35

N/C

No Connection

7

N/C

No Connection

34

N/C

No Connection

8

N/C

No Connection

33

N/C

9

VGUARD

Guard Ring

32

N/C

10

VSUB

Substrate

31

N/C

No Connection

11

VDD2

High Sensitivity Two-Stage Amplifier Supply

30

VGUARD

Guard Ring

12

VOUT2

Video Output from High Sensitivity Two-Stage Amplifier

29

VSUB

Substrate

13

VLG

First Stage Load Transistor Gate for Two-Stage Amplifier

28

φV1

Vertical (Parallel) CCD Clock - Phase 1

14

VSS

High Sensitivity Two-Stage Amplifier Return

27

φV2

Vertical (Parallel) CCD Clock - Phase 2

15

VRD

Reset Drain

26

φH1

Horizontal (Serial) CCD Clock - Phase 2

16

φR

Reset Clock

25

φH2

Horizontal (Serial) CCD Clock - Phase 1

17

VDD1

High Dynamic Range Single-Stage Amplifier Supply

24

φH22

Last Horizontal (Serial) CCD Phase - Split

Gate

18

VOUT1

Video Output from High Dynamic Range Single-Stage

Amplifier

23

φH21

Last Horizontal (Serial) CCD Phase - Split

Gate

19

VOG

Output Gate

22

VGUARD

Guard Ring

20

VSUB

Substrate

21

VSUB

Substrate

Notes:

1.

Pins 1, 2, 27, 39 and 40 must be connected together - only one Phase 2-clock driver is required.

2.

Pins 3, 4, 28, 37 and 38 must be connected together - only one Phase 1-clock driver is required.

3.

Pins 5, 10, 20, 21, 29 and 36 should be connected to a common potential.

4.

Pins 9, 22 and 30 should be connected to a common potential.