KAI-02050-ABA-JD-BA datasheet(6/41 Pages) ONSEMI

Part #	KAI-02050-ABA-JD-BA

Description	Interline CCD Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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KAI−02050

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Table 4. PGA PACKAGE PIN DESCRIPTION (continued)

Name

Description

25

Rb

Reset Gate, Quadrant b

26

RDb

Reset Drain, Quadrant b

27

GND

Ground

28

VOUTb

Video Output, Quadrant b

29

VDDb

Output Amplifier Supply, Quadrant b

30

V2B

Vertical CCD Clock, Phase 2, Bottom

31

V1B

Vertical CCD Clock, Phase 1, Bottom

32

V4B

Vertical CCD Clock, Phase 4, Bottom

33

V3B

Vertical CCD Clock, Phase 3, Bottom

34

ESD

ESD Protection Disable

35

V3T

Vertical CCD Clock, Phase 3, Top

36

DevID

Device Identification

37

V1T

Vertical CCD Clock, Phase 1, Top

38

V4T

Vertical CCD Clock, Phase 4, Top

39

VDDd

Output Amplifier Supply, Quadrant d

40

V2T

Vertical CCD Clock, Phase 2, Top

41

GND

Ground

42

VOUTd

Video Output, Quadrant d

43

Rd

Reset Gate, Quadrant d

44

RDd

Reset Drain, Quadrant d

45

H2SLd

Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d

46

OGd

Output Gate, Quadrant d

47

H1Bd

Horizontal CCD Clock, Phase 1, Barrier, Quadrant d

48

H2Bd

Horizontal CCD Clock, Phase 2, Barrier, Quadrant d

49

H2Sd

Horizontal CCD Clock, Phase 2, Storage, Quadrant d

50

H1Sd

Horizontal CCD Clock, Phase 1, Storage, Quadrant d

51

N/C

No Connect

52

SUB

Substrate

53

H2Sc

Horizontal CCD Clock, Phase 2, Storage, Quadrant c

54

H1Sc

Horizontal CCD Clock, Phase 1, Storage, Quadrant c

55

H1Bc

Horizontal CCD Clock, Phase 1, Barrier, Quadrant c

56

H2Bc

Horizontal CCD Clock, Phase 2, Barrier, Quadrant c

57

H2SLc

Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c

58

OGc

Output Gate, Quadrant c

59

Rc

Reset Gate, Quadrant c

60

RDc

Reset Drain, Quadrant c

61

GND

Ground

62

VOUTc

Video Output, Quadrant c

63

VDDc

Output Amplifier Supply, Quadrant c

64

V2T

Vertical CCD Clock, Phase 2, Top

65

V1T

Vertical CCD Clock, Phase 1, Top

66

V4T

Vertical CCD Clock, Phase 4, Top

67

V3T

Vertical CCD Clock, Phase 3, Top

68

ESD

EDS Protection Disable

1. Liked named pins are internally connected and should have a common drive signal.

2. N/C pins (17, 51) should be left floating.

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KAI-02050-ABA-JD-BA Datasheet(PDF) 6 Page - ON Semiconductor

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