NB3L8504SDTR2G datasheet(5/11 Pages) ONSEMI

Part #	NB3L8504SDTR2G

Description	2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer

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NB3L8504S

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Table 6. AC CHARACTERISTICS VDD = 2.5 V ± 5% or 3.3 V ± 10%; GND = 0 V; TA = −40°C to 85°C (Note 12) (Figure 10)

Symbol

Characteristic

Min

Typ

Max

Unit

fMAX

Input Clock Frequency

VOUTPP ≥ 250 mV @ VINPPmax

700

MHz

VOUTPP

Output Voltage Amplitude (@ VINPPmin) fin ≤ 700 MHz

(See Figure 3)

250

350

mV

tpd

Differential Input to Differential Output Propagation Delay at fMAX

@ VDD = 3.3 V

0.9

1.3

ns

tjit(f)

Additive Phase Jitter RMS (Figure 4)

fout = 156.25 MHz

Integration Range:12 kHz − 20 MHz

fout = 100 MHz

0.07

0.10

0.08

0.105

ps

tSKEW(o−o)

Output−to−output Skew (Note 14) (Figure 8)

50

ps

TSKEW(pp)

Part−to−part Skew (Note 14)

350

ps

tr / tf

Output Rise/Fall Times @ 50 MHz, 20% − 80%

180

350

660

ps

tDC

Output Clock Duty Cycle (Input Duty Cycle = 50%)

45

50

55

%

VINPP

Input Voltage Swing

(Differential Configuration) (Note 13)

150

1300

mV

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

12.Measured by forcing a 50% duty cycle clock source. All LVDS output loading with an external RL = 100 W across Q & Q.

13.VINPP(max) cannot exceed VDD. Input voltage swing is a single−ended measurement operating in differential mode.

14.Skew is measured between outputs under identical transition at 50 MHz.

Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) and Temperature (@ VDD = 2.5 V)

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