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KAF-8300-CXB-CB-AA Datasheet(PDF) 5 Page - ON Semiconductor |
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KAF-8300-CXB-CB-AA Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 28 page  KAF−8300 www.onsemi.com 5 non-uniformities. The response of these pixels will not be uniform. For monochrome devices, 20 buffer pixels adjacent to the dark dummy pixels are classified as active buffer pixels. These pixels are light sensitive but they are not tested for defects and non-uniformities. The response of these pixels will not be uniform. Blue Pixel Buffer For color devices, four buffer pixels adjacent to any leading or trailing dark reference regions contain a blue filter and is classified as a blue pixel buffer. These pixels are light sensitive but they are not tested for defects and non-uniformities. The response of these pixels will not be uniform. Monochrome devices do not contain a blue pixel buffer. CTE Monitor Pixels Within the horizontal dummy pixel region two light sensitive test pixels (one each on the leading and trailing ends) are added and within the vertical dummy pixel region one light sensitive test pixel has been added. These CTE monitor pixels are used for manufacturing test purposes. In order to facilitate measuring the device CTE, the pixels in the CTE Monitor region in the horizontal and vertical portion is coated with blue pigment on the color version only. The monochrome device is uncoated). Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the device. These photon-induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel’s capacity is reached, excess electrons are discharged into the lateral overflow drain to prevent crosstalk or ‘blooming’. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. Charge Transport The integrated charge from each photogate is transported to the output using a two-step process. Each line (row) of charge is first transported from the vertical CCD’s to a horizontal CCD register using the V1 and V2 register clocks. The horizontal CCD is presented a new line on the falling edge of V2 while H1 is held high. The horizontal CCD’s then transport each line, pixel by pixel, to the output structure by alternately clocking the H1 and H2 pins in a complementary fashion. A separate connection to the last H1 phase (H1L) is provided to improve the transfer speed of charge to the floating diffusion. On each falling edge of H1 a new charge packet is dumped onto a floating diffusion and sensed by the output amplifier. Horizontal Register Output Structure Charge presented to the floating diffusion (FD) is converted into a voltage and is current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the FD. Once the signal has been sampled by the system electronics, the reset gate (RG) is clocked to remove the signal and FD is reset to the potential applied by reset drain (RD). Increased signal at the floating diffusion reduces the voltage seen at the output pin. To activate the output structure, an off-chip load must be added to the VOUT pin of the device. See Figure 5. |
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