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KAI-18000 Datasheet(PDF) 7 Page - ON Semiconductor |
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KAI-18000 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 51 page KAI-18000 Image Sensor www.truesenseimaging.com Revision 3.1 PS0067 Pg 7 Device Description ARCHITECTURE Figure 1: Sensor Architecture To allow for 30 fps video with a 17 MHz pixel rate, there must be 40 outputs. There are twenty outputs across the top and twenty outputs across the bottom of the image sensor. The vertical CCD (VCCD) is split in half. The pixel design in the top half is an exact mirror image of the bottom half pixel design. The horizontal CCD (HCCD) on each half is split into 20 blocks, each 216 columns wide. The end of each block turns within the space of one column towards an output amplifier. There are six dummy HCCD pixels between the output amplifier and the imaging array. After each VCCD clock cycle one line will be transferred into each HCCD block. Once the HCCD clocks are started after the VCCD line transfer, the first six clock cycles will transfer empty charge packets to the output amplifier. Those are then followed by 216 clock cycles containing valid image data. There is no dead space between each HCCD block. There also are no dark columns on the image sensor. Dark columns are not possible on a HCCD with more than two outputs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 |
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