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4H0261 Datasheet(PDF) 11 Page - ON Semiconductor |
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4H0261 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 51 page KAI-18000 Image Sensor www.truesenseimaging.com Revision 3.1 PS0067 Pg 11 VERTICAL TO HORIZONTAL TRANSFER Figure 5: Vertical to Horizontal Transfer Architecture When the V1 and V2 timing inputs are clocked, charge in every pixel of the VCCD is shifted one row towards the HCCD. The last row of gates next to the HCCD has a separate clock line, VH. The timing requirements to meet 30 frames/sec mandate a very short horizontal retrace time which is insufficient to allow a complete VCCD transfer across the entire pixel array. To allow enough time for VCCD charge transfer the V1 and V2 clocks are operated during HCCD read out. This extends the V1 and V2 charge transfer times out to the length of one line time. To prevent charge from the VCCD from transferring into the HCCD during HCCD readout the last gate, VH, is clocked separately. VH is normally held low to block transfer from the VCCD to the HCCD. When an entire line has been read out of the HCCD and V1 is low and V2 is high, then VH is rapidly clocked from low to high and back low again in less than 1 µs. The short pulse on VH transfers the next row into the HCCD. H1 must be high and H2 must be low during the VH transfer time from the VCCD to the HCCD. V1 V2 V1 VH charge transfer H1 H2 H1 H2 |
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