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NB3H63143G Datasheet(PDF) 7 Page - ON Semiconductor |
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NB3H63143G Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 24 page NB3H63143G www.onsemi.com 7 Output Enable/Disable Output Enable pins (OE[2:0]) are LVCMOS/LVTTL input pins that individually enable or disable the outputs CLK[2:0] respectively. These inputs only disable the output buffers thus not affecting the rest of the blocks on the device. When using a differential output, only the OE1 pin must be used to enable/disable the differential output (the OE0 pin will be ignored). The hardware OE pins have an effect only when the respective outputs are enabled in the configuration space. The output disable state can be set to high impedance (Hi−Z) or Low. Power Down Power saving mode can be activated though the power down PD# input pin. This input is an LVCMOS/LVTTL active Low Master Reset that disables the device and sets the outputs Low. By default it has an internal pull−down resistor. The device functions are disabled by default and when the PD# pin is pulled high the device functions are activated. Default Device State The NB3H63143G parts shipped from ON Semiconductor are blank, with no inputs/outputs programmed. The parts need to be programmed by the field sales or by a distributor or by the users themselves before they can be used. Programmable clock software downloadable from the ON Semiconductor website can be used along with the programming kit to achieve this purpose. For mass production, parts can be factory programmed with a customer qualified configuration and sourced from ON Semiconductor as a dash part number (Eg. NB3H63143G−01). Table 7. ATTRIBUTES Characteristic Value ESD Protection − Human Body Model 2 kV Internal Input Default State Pull Up/Down Resistor 50 k W Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) MSL1 Flammability Rating − Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125in Transistor Count 130k Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. ABSOLUTE MAXIMUM RATINGS (Note 2) Symbol Parameter Rating Unit VDD Positive Power Supply with Respect to Ground −0.5 to +4.6 V VI Input Voltage with Respect to Chip Ground −0.5 to VDD + 0.5 V TA Operating Ambient Temperature Range (Industrial Grade) −40 to +85 °C TSTG Storage Temperature −65 to +150 °C TSOL Max. Soldering Temperature (10 sec) 265 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm 32.3 24.22 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 3.6 °C/W TJ Junction Temperature 125 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). JESD51.7 type board. Back side Copper heat spreader area 100 sqmm, 2 oz (0.070mm) copper thichness. |
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