NB3N853501E

http://onsemi.com

2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

CLK_EN

CLK_SEL

nc

CLK1

nc

nc

nc

CLK0

Figure 2. Pinout Diagram (Top View)

Table 1. PIN DESCRIPTION

Number

Name

I/O

Open

Default

Description

1

Negative (Ground) Power Supply pin must be externally connected to

power supply to guarantee proper operation.

2

CLK_EN

LVCMOS /

LVTTL

Pullup

Synchronized Clock Enable when HIGH. When LOW, outputs are

disabled (Qx HIGH, Qx LOW)

3

CLK_SEL

LVCMOS /

LVTTL

Pulldown

Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input)

4

CLK0

LVCMOS /

LVTTL

Pulldown

Clock 0 Input. Float open when unused.

5, 6, 8, 9

nc

No Connect

6

CLK1

LVCMOS /

LVTTL

Pulldown

Clock 1 Input. Float open when unused.

10, 13, 18

Positive Power Supply pins must be externally connected to power

supply to guarantee proper operation.

11, 14, 16,

19

Q[3:0]

LVPECL

Invert Differential Outputs

12, 15, 16,

20

Q[3:0]

LVPECL

True Differential Outputs

Table 2. FUNCTIONS

Inputs

Outputs

CLK_EN

CLK_SEL

Input Function

Output Function

Qx

Qx

0

0

CLK0 input selected

Disabled

LOW

HIGH

0

1

CLK1 Input Selected

Disabled

LOW

HIGH

1

0

CLK0 input selected

Enabled

CLK0

Invert of

CLK1

1

1

CLK1 Input Selected

Enabled

CLK1

Invert of

CLK1

1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.