UCC28610D datasheet(6/48 Pages) TI

Part #	UCC28610D

Description	Green-Mode Flyback Controller

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Manufacturer	TI [Texas Instruments]

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UCC28610

SLUS888G – JANUARY 2009 – REVISED SEPTEMBER 2015

www.ti.com

6.4 Thermal Information

UCC28610

THERMAL METRIC (1)

D (SOIC)

P (PDIP)

UNIT

8 PINS

RθJA

Junction-to-ambient thermal resistance

117.5

56.3

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

63.7

45.7

°C/W

RθJB

Junction-to-board thermal resistance

57.8

33.5

°C/W

ψJT

Junction-to-top characterization parameter

15.3

22.9

°C/W

ψJB

Junction-to-board characterization parameter

57.3

33.4

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise stated: VDD = 12 V, VGG = 12 V, ZCD = 1 V, IFB = 10 µA, GND = 0 V, a 0.1-μF capacitor between VDD

and GND, a 0.1-

μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ, –40°C < TA < +125°C, TJ = TA

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD and VGG SUPPLY

VGG(OPERATING)

VGG voltage, operating

VDD = 14 V, IVGG = 2.0 mA

13

14

15

V

VGG(DISABLED)

VGG voltage, PWM disabled

VDD = 12 V, IVGG = 15 μA, IFB = 350 μA

15

16

17

V

Rise in VGG clamping voltage

ΔVGG

VGG(DISABLED) – VGG(OPERATING)

1.75

2.00

2.15

V

during UVLO, GM, or Fault

VGG = VGG(DISABLED) -100 mV, VDD = 12

IVGG(SREG)

VGG shunt regulator current

6

10

μA

V

ΔVGG(SREG)

VGG shunt load regulation

10

μA ≤ IVGG ≤ 5 mA, IFB = 350 μA

125

200

mV

VGG(LREG)

VGG LDO regulation voltage

VDD = 20 V, IVGG = – 2 mA

13

V

VGG(LREG, DO)

VGG LDO Dropout Voltage

VDD – VGG, VDD = 11 V, IVGG = – 2 mA

1.5

2

2.5

V

VDD(ON)

UVLO turn-on threshold

9.7

10.2

10.7

V

VDD(OFF)

UVLO turn-off threshold

7.55

8

8.5

V

ΔVDD(UVLO)

UVLO hysteresis

1.9

2.2

2.5

V

IVDD(OPERATING)

Operating current

VDD = 20 V

2.5

3

3.7

mA

IVDD(GM)

Idle current between bursts

IFB = 350 μA

550

900

μA

IVDD(UVLO)

Current for VDD < UVLO

VDD = VDD(ON) – 100 mV, increasing

225

310

μA

VDD Switch on resistance, DRV to

RDS,ON(VDD)

VGG = 12 V, VDD = 7V, IDRV = 50 mA

4

10

Ω

VDD

VDD(FAULT RESET)

VDD for fault latch reset

5.6

6

6.4

V

MODULATION

Minimum switching period,

tS(HF)

(1)

IFB = 0 μA,

(1)

7.125

7.5

7.875

μs

frequency modulation (FM) mode

Maximum switching period,

tS(LF)

(1)

reached at end of FM modulation

IFB = IFB, CNR3 – 20 μA,

(1)

31

34

38

μs

range

IFB = 0 μA, RCL = 33. 2 kΩ

2.85

3

3.15

Maximum peak driver current over

IDRVpk(max)

A

amplitude modulation(AM) range

IFB = 0 μA, RCL = 100 kΩ

0.80

0.90

1.0

Minimum peak driver current

IFB, CNR2 + 10 μA, RCL = 33.2 kΩ

0.7

0.85

1.1

IDRVpk(min)

reached at end of AM modulation

A

IFB, CNR2 + 10 μA, RCL = 100 kΩ

0.2

0.33

0.5

range

KP

Maximum power constant

IDRVpk(max) = 3 A

0.54

0.60

0.66

W/

μH

Minimum peak driver independent

IDRVpk(absmin)

RCL = OPEN

0.3

0.45

0.6

A

of RCL or AM control

(1)

tS sets a minimum switching period. Following the starting edge of a PWM on time, under normal conditions, the next on time is initiated

following the first zero crossing at ZCD after tS. The value of tS is modulated by IFB between a minimum of tS(HF) and a maximum of

tS(LF) In normal operation, tS(HF) sets the maximum operating frequency of the power supply and tS(LF) sets the minimum operating

frequency of the power supply.

6

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