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TPS566250DDAR Datasheet(PDF) 5 Page - Texas Instruments |
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TPS566250DDAR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 32 page  TPS566250 www.ti.com SLVSCV3B – MARCH 2015 – REVISED JUNE 2015 7.5 Electrical Characteristics Over operating junction temperature range, VIN = 12 V (Unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IIN VIN supply current TA = 25°C, EN = 5 V, FB = 0.7 V (non switching) 450 525 µA I(VINSDN) VIN shutdown current TA = 25°C, EN = 0 V 6.5 10 µA LOGIC THRESHOLD V(ENH) EN H-level threshold voltage 1.1 1.6 V V(ENL) EN L-level threshold voltage 0.6 0.94 V Hystersis 160 mV R(EN) EN pin resistance to GND V(EN) = 12 V 225 350 800 k Ω FEEDBACK VOLTAGE TA = 0°C to 85°C VOUT = 1.1 V, Upper/lower feedback resistors: –1.6% 0 1.6% 1.37 k Ω / 1.65 kΩ V(FB) FB voltage TA = 25°C, VOUT = 1.1 V, IOUT = 10 mA, pulse 0.606 V skipping TA = 25°C, VOUT = 1.1 V, continuous current mode 0.594 0.6 0.606 V MOSFET rDS(on)H High side switch resistance BOOT - SW = 5.5 V 44 74 m Ω rDS(on)L Low side switch resistance VIN = 12 V 23 35 m Ω Discharge FET 200 Ω ON-TIME TIMER CONTROL fsw Switching frequency LOUT = 1.5 µH, COUT = 22 µF x 2, VOUT = 1.1 V 650 kHz CURRENT LIMIT Valley current limit LOUT = 1.5 µH, VOUT = 1.1 V, VIN = 12 V 7.6 9.5 11.4 A IOCL Reverse valley current limit LOUT = 1.5 µH, VOUT = 1.1 V 1.5 4.5 7 A OUTPUT UNDERVOLTAGE PROTECTION V(UVP) Output UVP trip threshold UVP detect (H > L) 65% THERMAL SHUTDOWN Shutdown temperature(1) 165 °C TSDN Thermal shutdown Threshold Hysteresis(1) 15 °C UVLO VIN rising voltage 3.26 3.75 4.05 V UVLO UVLO Threshold Hysteresis VIN voltage 0.13 0.33 0.48 V PGOOD VIA I2C FB falling (fault) VO = 1.1 V 80% FB rising (good) VO = 1.1 V 85% V(PGOODTH) PGOOD threshold FB rising (fault) VO = 1.1 V 125% FB falling (good) VO = 1.1 V 120% SERIAL INTERFACE(1) (2) (3) VIL LOW level input voltage 0.6 V VIH HIGH level input voltage 1.85 V Vhys Hysteresis of schmitt trigger inputs 0.11 V LOW level output voltage VOL 0.4 V (Open drain, 3 mA sink current) fSCL SCL clock frequency 400 kHz Cb Capacitive load for each bus line 400 pF (1) Specified by design. Not production tested. (2) Refer to Figure 1 for I2C Timing Definitions (3) Cb = capacitance of bus line in pF Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS566250 |
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