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AR023ZMCSC00SUEAD3-GEVK Datasheet(PDF) 8 Page - ON Semiconductor |
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AR023ZMCSC00SUEAD3-GEVK Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 35 page AR0230CS_DS Rev. 4 Pub. 8/15 EN 8 ©Semiconductor Components Industries, LLC, 2015. AR023ZM: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview ON Semiconductor Confidential and Proprietary high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 16-bit per pixel value. A compression mode is further offered to allow the 16 bits per pixel to be transmitted to the host system as a 12-bit value with close to zero loss in image quality. Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. The parallel interface output pads can be left unconnected if the serial output interface is used. 4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR023ZM demo headboard schematics for circuit rec- ommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. VDD_IO VDD_SLVS VDD_PLL VDD VAA VDD VAA VAA_PIX Master clock (6–48 MHz) SDATA SCLK RESET_BAR TEST EXTCLK DGND AGND Digital ground Analog ground Digital Core power1 HiSPi power1 Analog power1 To controller From controller VDD_IO VDD_PLL PLL power1 Digital I/O power1 Analog power1 VAA_PIX SLVSC_N SLVSC_P SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SLVS3_P SLVS3_N TRIGGER OE_BAR SADDR SHUTTER FLASH |
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