LC87F2932A

No.A1210-3/29

UART

• Full duplex

• 7/8/9 bit data bits selectable

• 1 stop bit (2-bit in continuous data transmission)

• Built-in baudrate generator

AD Converter: 8 bits

× 13 channels

PWM: Multifrequency 12-bit PWM

× 2 channels

Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)

• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)

Watchdog Timer

• External RC watchdog timer

• Interrupt and reset signals selectable

Clock Output Function

1) Outputs clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock of the system clock

2) Outputs clock of the subclock

Interrupts

• 26 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests

of the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4

4

0001BH

H or L

INT3/INT5/ BT0/BT1/DHMSC

5

00023H

H or L

T0H/INT6

6

0002BH

H or L

T1L/T1H/INT7

7

00033H

H or L

SIO0/UART1 receive

8

0003BH

H or L

SIO1/UART1 transmit

9

00043H

H or L

ADC/T6/T7

10

0004BH

H or L

Port 0/T4/T5/PWM2, PWM3

• Priority levels X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

• IFLG (List of interrupt source flag function)

1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table

above).

Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

(5 tCYC execution time)

• 24 bits × 16 bits

(12 tCYC execution time)

• 16 bits ÷ 8 bits

(8 tCYC execution time)

• 24 bits ÷ 16 bits

(12 tCYC execution time)