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LC87FBK08A Datasheet(PDF) 3 Page - ON Semiconductor |
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LC87FBK08A Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 28 page LC87FBK08A No.A1956-3/28 Interrupts • 15 sources, 9 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L None 8 0003BH H or L SIO1 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • Internal oscillation circuits Low-speed RC oscillation circuit (SRC): For system clock / For Watchdog timer (100kHz) Medium-speed RC oscillation circuit (RC): For system clock (1MHz) Frequency variable RC oscillation circuit (MRC): For system clock (8MHz ±2.5%, Ta=-10°C to +85°C) • External oscillation circuits Hi-speed CF oscillation circuit (CF): For system clock, with internal Rf Low speed crystal oscillation circuit (X’tal): For low-speed system clock / For Watchdog timer, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) Both the CF and crystal oscillator circuits stop operation on a system reset. After reset is released, oscillation is stopped so start the oscillation operation by program. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8 μs (at a main clock rate of 10MHz). Internal Reset Function • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 4 levels (2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V, 4.28V) can be selected by optional configuration. |
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