LX8386-xx/8386A-xx/8386B-xx

PRODUCT DA T ABOOK 1996/1997

Copyright © 1999

Rev. 1.7a 10/00

2

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Power Dissipation .................................................................................. Internally Limited

Input Voltage ................................................................................................................ 10V

Input to Output Voltage Differential ........................................................................... 10V

Maximum Output Current .......................................................................................... 1.5A

Operating Junction Temperature

Plastic (P, DD & DT Packages) ............................................................................ 150°C

Storage Temperature Range ...................................................................... -65°C to 150°C

Lead Temperature (Soldering, 10 seconds) ............................................................. 300°C

PACKAGE PIN OUTS

P PACKAGE

(Top View)

* Pin 1 is GND for fixed voltage versions.

DD PACKAGE

(Top View)

* Pin 1 is GND for fixed voltage versions.

Note 1. Exceeding these ratings could cause damage to the device. All voltages are with

respect to Ground. Currents are positive into, negative out of the specified terminal.

P PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JT

3.0°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

60°C/W

DD PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JT

3.0°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

*60°C/W

DT PACKAGE:

THERMAL RESISTANCE-JUNCTION TO TAB,

θθθθθ

JT

9°C/W

THERMAL RESISTANCE-JUNCTION TO AMBIENT,

θθθθθ

JA

*80°C/W

Junction Temperature Calculation: T

The

θ

JA

numbers are guidelines for the thermal performance of the device/pc-board system. All

of the above assume no ambient airflow.

*

θ

plane or internal power plane.

θ

mounting technique.

THERMAL DATA

BLOCK DIAGRAM

Thermal

Limit Circuit

Control

Circuit

Bandgap

Circuit

Output

Circuit

Bias

Circuit

V

OUT

V

IN

SOA Protection

Circuit

Current

Limit Circuit

ADJ or

GND*

3

2

1

3

2

1

TAB IS V

OUT

TAB IS V

OUT

* This pin GND for fixed voltage versions.

3. V

IN

2. V

OUT

1. ADJ / GND*

DT PACKAGE (D-Pak)

(Top View)

* Pin 1 is GND for fixed voltage versions.

TAB IS V

OUT

V

IN

V

OUT

ADJ / GND*

V

IN

V

OUT

ADJ / GND*