LE25U81AFD

No.A2263-3/23

AC Characteristics

Parameter

Symbol

Ratings

unit

min

typ

max

Clock frequency

Read instruction (03h)

fCLK

30

MHz

All instruction except for read (03h)

40

MHz

Input signal rising/falling time

tRF

0.1

V/ns

SCK logic high level pulse width

30MHz

tCLHI

14

ns

40MHz

11.5

ns

SCK logic low level pulse width

30MHz

tCLLO

14

ns

40MHz

11.5

ns

CS setup time

tCSS

10

ns

Data setup time

tDS

5

ns

Data hold time

tDH

4

ns

CS hold time

tCSH

10

ns

CS wait pulse width

tCPH

25

ns

Output high impedance time from CS

tCHZ

15

ns

Output data time from SCK

tV

8

9

ns

Output data hold time

tHO

1

ns

HOLD setup time

tHS

5

ns

HOLD hold time

tHH

5

ns

Output low impedance time from HOLD

tHLZ

12

ns

Output high impedance time from HOLD

tHHZ

9

ns

WP setup time

tWPS

20

ns

WP hold time

tWPH

20

ns

Write status register time

tSRW

8

10

ms

Page programming cycle time

256Byte

tPP

0.3

0.5

ms

nByte

0.15+

n*0.15/256

0.20+

n*0.30/256

ms

Small sector erase cycle time

tSSE

0.04

0.15

s

Sector erase cycle time

tSE

0.08

0.25

s

Chip erase cycle time

tCHE

0.5

6.0

s

Power-down time

tDP

5

s

Power-down recovery time

tPRB

500

s

Output low impedance time from SCK

tCLZ

0

ns

AC Test Conditions

Input pulse level ··········· 0.2VDD to 0.8VDD

Input rising/falling time ·· 5ns

Input timing level ········· 0.3VDD, 0.7VDD

Output timing level ······· 1/2

VDD

Output load ················ 15pF

Note: As the test conditions for "typ", the measurements are conducted using 2.5V for VDD at room temperature.

0.8VDD

0.2VDD

0.7VDD

0.3VDD

1/2VDD

input level

input/output timing level