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SN74LS161AM Datasheet(PDF) 2 Page - ON Semiconductor |
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SN74LS161AM Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS161A, SN74LS163A http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs Terminal Count Output PE P0 − P3 CEP CET CP MR SR Q0 − Q3 TC 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES VCC = PIN 16 GND = PIN 8 LOGIC SYMBOL NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 13 12 11 10 9 12345 6 7 16 15 8 VCC *R TC Q0 Q1 Q2 CET Q3 PE CP P0 P1 P2 P3 CEP GND 934 56 7 10 2 15 1 14 131211 PE P0 P1 P2 P3 CEP CET CP *R Q0 Q1 Q2 Q3 TC *MR for LS161A *SR for LS163A *MR for LS161A *SR for LS163A |
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