LC717A10PJ

No.A2214-7/14

When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset

time, tPOR. Power-on Reset operation condition; Power supply rise rate tVDD must be at least 1V/ms.

Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset, it is possible to

verify the timing of release of power-on reset externally.

During power-on reset, Cin, Cref and CrefAdd are unknown.

fig.1

I

fig.2

I

 Write format (data can be written into sequentially incremented addresses)

START

Slave Address

Write=L

Register Address (N)

ACK

ACK

Slave

Slave

Slave

Slave

fig.3

 Read format (data can be read from sequentially incremented addresses)

START

Slave Address

Write=L

Register Address (N)

ACK

ACK

Data read from Register Address (N)

ACK

RESTART

Slave Address

Read=H

ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2)

Slave

Slave

Slave

Master

Master

Master

fig.4

SDA

SCL

START

condition

tHD;STA

tLOW

tHIGH

tr

repeated START

condition

STOP

condition

10%

tf

90%

10% 10%

90% 90%

tHD;DTA tSU;DTA

10%

10%

10%

90%

tSU;STA

90%

90%

tHD;STA

90%

10%

90%

10%

90%

10%

tSU;STO

tBUF

START

condition

90%

POR

(LSI internal signal)

RELEASE

tPOR

VDD

RESET

tVDD

INTOUT

VPOROP

Cin,

Cref,

CrefAdd

UNKNOWN

VALID

tPOROP

UNKNOWN

UNKNOWN

UNKNOWN

RESET

RELEASE

tPOR

VALID