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SZESD8004MUTAG Datasheet(PDF) 2 Page - ON Semiconductor |
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SZESD8004MUTAG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 11 page ESD8004 www.onsemi.com 2 See Application Note AND8308/D for further description of survivability specs. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter VRWM Working Peak Voltage IR Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT Test Current VHOLD Holding Reverse Voltage IHOLD Holding Reverse Current RDYN Dynamic Resistance IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VC = VHOLD + (IPP * RDYN) I V VCVRWMVHOLD VBR RDYN VC IR IT IHOLD −IPP RDYN IPP VC = VHOLD + (IPP * RDYN) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM I/O Pin to GND 3.3 V Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 7.0 V Reverse Leakage Current IR VRWM = 3.3 V, I/O Pin to GND 1.0 mA Holding Reverse Voltage VHOLD I/O Pin to GND 1.19 V Holding Reverse Current IHOLD I/O Pin to GND 25 mA Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 KV Contact See Figures 1 and 2 V Clamping Voltage TLP (Note 2) See Figures 5 through 8 VC IPP = 8 A IPP = −8 A IEC 61000−4−2 Level 2 equivalent (±4 kV Contact, ±4 kV Air) 4.9 −4.5 V IPP = 16 A IPP = −16 A IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) 8.0 −8.0 Dynamic Resistance RDYN I/O Pin to GND GND to I/O Pin 0.40 0.45 W Junction Capacitance (See Figures 9 & 10) CJ VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 2.5 GHz between I/O Pins and GND VR = 0 V, f = 1 MHz, between I/O Pins 0.30 0.25 0.15 0.35 0.30 0.20 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For test procedure see Figures 3 and 4 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −20 0 20 40 60 80 100 140 120 Figure 1. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Figure 2. IEC61000−4−2 −8 kV Contact Clamping Voltage −20 0 20 40 60 80 100 140 120 90 TIME (ns) TIME (ns) 80 70 60 50 40 30 20 10 0 −10 10 |
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