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NSBA114TDXV6T5G Datasheet(PDF) 1 Page - ON Semiconductor |
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NSBA114TDXV6T5G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 0 1 Publication Order Number: DTA114TD/D MUN5115DW1, NSBA114TDXV6, NSBA114TDP6 Dual PNP Bias Resistor Transistors R1 = 10 kW, R2 = 8 kW PNP Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. Features Simplifies Circuit Design Reduces Board Space Reduces Component Count S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (TA = 25C, common for Q1 and Q2, unless otherwise noted) Rating Symbol Max Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current − Continuous IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc Input Reverse Voltage VIN(rev) 5 Vdc Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION Device Package Shipping† MUN5115DW1T1G, SMUN5115DW1T1G SOT−363 3,000/Tape & Reel NSBA114TDXV6T1G SOT−563 4,000/Tape & Reel NSBA114TDXV6T5G SOT−563 8,000/Tape & Reel NSBA114TDP6T5G SOT−963 8,000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com MARKING DIAGRAMS PIN CONNECTIONS 0E M G G 1 6 0E M G G 1 0E/T = Specific Device Code M = Date Code* G = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. SOT−363 CASE 419B SOT−563 CASE 463A Q1 Q2 (1) (2) (3) (6) (5) (4) R1 R2 R2 R1 SOT−963 CASE 527AD MG G 1 |
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