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NB3N106K Datasheet(PDF) 7 Page - ON Semiconductor |
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NB3N106K Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 10 page NB3N106K http://onsemi.com 7 Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation A. Connect 475 W resistor RREF from IREF pin to GND. B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit. D. DL1, DL2 Termination and Load Resistors Located at Received Inputs. CL1C 2 pF CL2C 2 pF Z0 = 50 W Z0 = 50 W Receiver RS1B RS2B HCSL Driver RREFA RL1D 50 W RL2D 50 W Qx Qx IREF 50 W* VTCLK = VTCLK = VCC − 2.0 V LVPECL Driver Z0 = 50 W Z0 = 50 W VCC = 3.3 V / 2.5 V VCC = 3.3 V GND GND 50 W* VTCLK VTCLK Figure 7. LVPECL Interface *RTIN, Internal Input Termination Resistor 50 W* VTCLK = VTCLK LVDS Driver Z0 = 50 W Z0 = 50 W VCC = 3.3 V / 2.5 V / 1.8 V VCC = 3.3 V GND GND 50 W* VTCLK VTCLK Figure 8. LVDS Interface *RTIN, Internal Input Termination Resistor NB3N106K NB3N106K CLK CLK CLK CLK |
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