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ASM3I622S00EF-16-ST Datasheet(PDF) 2 Page - ON Semiconductor

Part # ASM3I622S00EF-16-ST
Description  Low Frequency Peak EMI Reduction IC
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ASM3I622S00EF-16-ST Datasheet(HTML) 2 Page - ON Semiconductor

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ASM3P622S00B, ASM3P622S00E
http://onsemi.com
2
Figure 1. General Block Diagram
SS%
DLY_CTRL
VDD
GND
SSON
PLL
CLKIN
CLKOUT(s)*
(Timing−Safe)
*For ASM3P622S00E −
8 CLKOUTS
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P622S00B/E
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified modulation
rate. With center modulation, the average frequency is the
same as the unmodulated frequency and there is no
performance degradation.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.


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