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MT8841AE Datasheet(PDF) 2 Page - Mitel Networks Corporation |
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MT8841AE Datasheet(HTML) 2 Page - Mitel Networks Corporation |
2 / 10 page MT8841 5-12 Figure 2 - Pin Connections Pin Description Pin # Name Description 16 20 11 IN+ Non-inverting Op-Amp (Input). 22 IN- Inverting Op-Amp (Input). 33 GS Gain Select (Output). Gives access to op-amp output for connection of feedback resistor. 44 VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs. 55 CAP Capacitor. Connect a 0.1µF capacitor to VSS. 67 OSC1 Oscillator (Input). Crystal or ceramic resonator connection. This pin can be driven directly from an external clocking source. 79 OSC2 Oscillator (Output). Crystal or ceramic resonator connection. When OSC1 is driven by an external clock, this pin should be left open. 810 VSS Power supply ground. 9 11 DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a serial-to-parallel converter. 10 12 DATA Data (Output). Serial data output corresponding to the FSK input and switching at the input baud rate. Mark frequency at the input corresponds to a logic high, while space frequency corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This output stays high until CD has become active. 11 13 DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each word. This can be used to identify the data (8-bit word) boundary on the serial output stream. Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a microcontroller. 12 14 CD Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity of carrier. 13 15 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the input op-amp and the oscillator. 14 16 IC1 Internal Connection 1. Connect to VSS. 15 19 IC2 Internal Connection 2. Internally connected, leave open circuit. 16 20 VDD Positive power supply voltage. 6,8 17, 18 NC No Connection. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN+ IN- GS VRef CAP OSC1 OSC2 VSS VDD IC2 IC1 PWDN CD DR DATA DCLK 16 PIN PLASTIC DIP/SOIC 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 IN+ IN- GS VRef CAP NC OSC1 NC OSC2 VSS 20 PIN SSOP VDD IC2 NC NC PWDN CD DR DATA DCLK IC1 |
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