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MT8880CN-1 Datasheet(PDF) 4 Page - Mitel Networks Corporation |
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MT8880CN-1 Datasheet(HTML) 4 Page - Mitel Networks Corporation |
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4 / 18 page  MT8880C/MT8880C-1 ISO2-CMOS 4-36 Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Figure 7) into the Receive Data Register. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Figure 5 - Basic Steering Circuit VDD VDD St/GT ESt C1 Vc R1 MT8880C/C-1 tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)] Guard Time Adjustment The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the formula: tREC = tDP+tGTP tID=tDA+tGTA The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Figure 6 - Guard Time Adjustment VDD St/GT ESt VDD St/GT ESt C1 R1 R2 C1 R1 R2 tGTA = (R1C1) In (VDD/VTSt) tGTP = (RPC1) In [VDD / (VDD-VTSt)] RP = (R1R2) / (R1 + R2) tGTA = (RpC1) In (VDD/VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt) RP = (R1R2) / (R1 + R2) a) decreasing tGTP; (tGTP < tGTA) b) decreasing tGTA; (tGTP > tGTA) |
Similar Part No. - MT8880CN-1 |
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Similar Description - MT8880CN-1 |
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