MT8888C/MT8888C-1

4-100

Table 8

Figure 12 - MT8888C Interface Connections for Various Intel Micros

Figure 13 - Application Circuit (Single-Ended Input)

BIT

NAME

STATUS FLAG SET

STATUS FLAG CLEARED

b0

IRQ

Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

Interrupt is inactive. Cleared after

Status Register is read.

b1

TRANSMIT DATA

REGISTER EMPTY

(BURST MODE ONLY)

Pause duration has terminated

and transmitter is ready for new

data.

Cleared after Status Register is

read or when in non-burst mode.

b2

RECEIVE DATA REGISTER

FULL

Valid data is in the Receive Data

Register.

Cleared after Status Register is

read.

b3

DELAYED STEERING

Set upon the valid detection of

the absence of a DTMF signal.

Cleared upon the detection of a

valid DTMF signal.

8031/8051

8080/8085

MT8888C/MT8888C-1

A8-A15

PO

RD

WR

CS

RD

WR

RS0

D0-D3

A8

IN+

IN-

GS

VRef

VSS

OSC1

OSC2

TONE

WR

CS

VDD

St/GT

ESt

D3

D2

D1

D0

IRQ/CP

RD

RS0

DTMF/CP

INPUT

DTMF

OUTPUT

C1

R1

R2

X-tal

C3

C2

R4

R3

To

µP

or

µC

Notes:

R1, R2 = 100 k

Ω 1%

R3 = 374

Ω 1%

R4 = 3.3 k

Ω 10%

C1 = 100 nF 5%

C2 = 100 nF 5%

C3 = 100 nF 10%*

X-tal = 3.579545 MHz

* Microprocessor based systems can inject undesirable noise into the supply rails.

The performance of the MT8888C/MT8888C-1 can be optimized by keeping

noise on the supply rails to a minimum. The decoupling capacitor (C3) should be

connected close to the device and ground loops should be avoided.

MT8888C/MT8888C-1