CMOS

MT8920B

3-9

Table 2. Mode 1 Address Map

NOTES:

X is don’t care

Table 3.

Control Register 1 Bit Definitions

ADDRESS BITS

REGISTERS

READ

WRITE

0

•

•

•

0

0

•

•

•

0

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

Rx0 - Channel 0

•

•

•

Rx0 - Channel 31

Tx0 - Channel 0

•

•

•

Tx0 - Channel 31

X

1

00000

Control Register 1

Control Register 1

X

1

00001

Control Register 2

Control Register 2

X

1

00010

Interrupt Vector Register

Interrupt Vector Register

X

1

00100

Interrupt Flag Register 1

-

X

1

00101

Interrupt Flag Register 2

-

X

1

00110

Image Register 1

-

X

1

00111

Image Register 2

-

X

1

01000

Interrupt Mask Register 1

Interrupt Mask Register 1

X

1

01001

Interrupt Mask Register 2

Interrupt Mask Register 2

X

1

01010

Match Byte Register 1

Match Byte Register 1

X

1

01011

Match Byte Register 2

Match Byte Register 2

X

1

01100

Interrupt Channel Address 1

Interrupt Channel Address 1

X

1

01101

Interrupt Channel Address 2

Interrupt Channel Address 2

1

•

•

•

1

0

•

•

•

0

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

0

•

•

•

1

Rx0 - Channel 0

•

•

•

Rx0 - Channel 31

Tx1 - Channel 0

•

•

•

Tx1 - Channel 31

Bit

Name

Description

7

(Unused)

6

IRQRST

Interrupt Reset. This bit, when set high, automatically clears the Interrupt Flag Register

and the Interrupt Image Register without these registers being serviced. This bit

automatically resets to zero after the register clear is completed.

5

RAMCON

RAM Configuration.

This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte

Address Bit A6.

This bit extends the addressing range for access to Tx1 memory.

3

IRQ2MODE

Interrupt Source 2 Mode Select. This bit configures the source 2 interrupt generator.

2

IRQ1MODE

Interrupt Source 1 Mode Select. This bit configures the source 1 interrupt generator.

1

IRQ2EN

Interrupt Source 2 Enable. IRQ2EN = 1 enables interrupts to occur from source 2.

0

IRQ1EN

Interrupt Source 1 Enable. IRQ1EN = 1 enables interrupts to occur from source 1.