MT8971B/72B

9-117

Table 4a. Default Mode Selection

Notes:

Table 5. Diagnostic Register

Notes:

Œ

When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.



Ž

Do not use DSTo to DSTi loopback in MOD/MAS mode.

C-Channel

(Bit 0-7)

Internal Control

Register

Internal Diagnostic

Register

Description

XXX01111

00000000

01000000

Default Mode-1

PSEN, DINB, DRR and all diagnostics are disabled.

TxHK=0.

XXX11111

00010000

01000000

Default Mode-2

PSEN, DINB, DRR and all diagnostics are disabled.

TxHK=0.

Bit

Name

Description

0

Reg Sel-1

Register Select-1. Must be set to ’0’ to select the Diagnostic Register.

1

Reg Sel-2

Register Select-2. Must be set to ’1’ to select the Diagnostic Register.

2,3

Loopback

Bit 2

Bit 3

0

0

All loopback testing functions disabled. Normal operation.

0

1

DSTi internally looped back into DSTo for system diagnostics.

10



1

1

DSTo is internally looped back into DSTi for end-to-end testing.

Ž

4FUN

Œ

Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC

recovery circuitry. When set to ’0’, the operation continues in synchronization.

5

PSWAP

Œ

Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials

are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain

their normal designations.

6DLO

Œ

7

Not Used

Must be set to ’0’ for normal operation.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1

Reg Sel-2

Loopback

FUN

PSWAP

DLO

Not Used

Default Mode Selection

(Refer to Table 4a)

and CLD with TCK defining the bits and CLD the

channel boundaries of the data stream as shown in

Figure 8.

receiving the composite transmit and receive signal

from the line. The line code used in the DNIC is

Biphase and is shown in Figure 10. The scrambled

NRZ data is differentially encoded meaning the

previous differential encoded output is XOR’d with

the current data bit which produces the current

output.

This

is

then

biphase

encoded

where

transitions occur midway through the bit cell with a

negative going transition indicating a logic "0" and a

positive going transition indicating a logic "1".