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MT8952 Datasheet(PDF) 1 Page - Mitel Networks Corporation |
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MT8952 Datasheet(HTML) 1 Page - Mitel Networks Corporation |
1 / 22 page 3-61 ® Features • Formats data as per X.25 (CCITT) level-2 standards • Go-Ahead sequence generation and detection • Single byte address recognition • Microprocessor port and directly accessible registers for flexible operation and control • 19 byte FIFO in both send and receive paths • Handshake signals for multiplexing data links • High speed serially clocked output (2.5 Mbps) • ST-BUS compatibility with programmable channel selection for data and separate timeslot for control information • Independent watchdog timer • Facility to disable protocol functions • Low power ISO-CMOS technology Applications • Data link controllers and protocol generators • Digital sets, PBXs and private packet networks • D-channel controller for ISDN basic access • C-channel controller to Digital Network Interface Circuits (typically MT8972) • Interprocessor communication Description The MT8952B HDLC Protocol Controller frames and formats data packets according to X.25 (Level 2) Recommendations from the CCITT. Ordering Information MT8952BC 28 Pin Ceramic DIP MT8952BE 28 Pin Plastic DIP MT8952BP 28 Pin PLCC MT8952BS 28 Pin SOIC -40 °C to 85°C Figure 1 - Functional Block Diagram D0-D7 A0-A3 R/W CS E IRQ WD VDD VSS RST TEOP CDSTo F0i CKi RxCEN TxCEN CDSTi REOP C-Channel Interface Micro Processor Interface Receive FIFO Transmit FIFO Transmit Logic Zero Insertion Flag/Abort Generator Address Decoder Interrupt Registers Control and Status Register Timing Logic Receive Logic Address Detection Zero Deletion Flag/Abort/ Idle Detection ISSUE 5 May 1995 MT8952B HDLC Protocol Controller ISO-CMOS ST-BUS ™ FAMILY |
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