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MT8977AP Datasheet(PDF) 3 Page - Mitel Networks Corporation |
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MT8977AP Datasheet(HTML) 3 Page - Mitel Networks Corporation |
3 / 26 page Preliminary Information ISO-CMOS MT8977 4-101 12 19 CSTi0 Control ST-BUS Input #0. A 2048 kbit/s serial control stream that contains 24 per channel control words and two master control words. 13 20 E8Ko Extracted 8 kHz Output. The E1.5i clock is internally divided by 193 to produce an 8 kHz clock which is aligned with the received DS1 frame and output at this pin. The 8 kHz signal is derived from C1.5 in Digital Loopback mode. 14 6, 18, 22 VSS System Ground. 15 23 XCtl External Control (Output). This is an uncommitted external output pin which is set or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per frame. 16 24 XSt External Status (Schmitt Trigger Input). The state of this pin is sampled once per frame and the status is reported in bit 5 of Master Status Word 2 on CSTo. 17 26 CSTo Control ST-BUS Output. This is a 2048 kbit/s serial control stream which provides the 24 per-channel status words, and two master status words. 18 27 RxFDLClk Receive Facility Data Link Clock (Output). A 4 kHz clock signal used to clock out FDL information. The data is clocked out on the rising edge of RxFDLClk. 19 28 DSTi Data ST-BUS Input. This pin accepts a 2048 kbit/s serial stream which contains the 24 PCM or data channels to be transmitted on the T1 trunk. 20 29 RxFDL Received Facility Data Link (Output). A 4 kHz serial output stream that is demultiplexed from the FDL in ESF mode, or the received Fs bit pattern in SLC-96 mode. It is clocked out on the rising edge of RxFDLClk. 21 34 C2i 2.048 MHz Clock Input. This is the master clock used for clocking serial data into DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo. 22 37 TxSF Transmit Superframe Pulse Input. A low going pulse applied at this pin will make the next transmit frame the first frame of a superframe. The device will free run if this pin is held high. 23 38 RxSF Received Superframe Pulse Output. A pulse output on this pin designates that the next frame of data on the ST-BUS is from frame 1 of the received superframe. The period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are output only when the device is synchronized to the received DS1 signal. 24 39 C1.5i 1.544 MHz Clock Input. This is the DS1 transmit clock and is used to output data on TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising edge of C1.5i. 25 40 E1.5i 1.544 MHz Extracted Clock (Input). This clock which is extracted from the received data is used to clock in data at RxA, RxB and RxD . The falling edge of the clock is nominally aligned with the center of the received bit on RxD, RxA and RxB. 26 42 F0i Frame Pulse Input. This is the frame synchronization signal which defines the beginning of the 32 channel ST-BUS frame. 27 44 IC Internal Connection. Tied to VSS for normal operation. 28 1 VDD Positive Power Supply Input. +5V ±5%. Pin Description (Continued) Pin # Name Description DIP PLCC |
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