MT8980D

2-10

Figure 8 - Example Architecture of a Simple Digital Switching System

Controlling

Micro-

Processor

Speech

Switch

-

8980

Control &

Signalling

-

8980

STo0-7

STi0-7

STo0-7

Line Interface Circuit

with Codec (e.g. 8964)

Line 1

Line 256

Line Interface Circuit

with Codec (e.g.8964)

8

8

8

8

•

•

•

Repeated for Lines

2 to 255

•

•

•

Repeated for Lines

2 to 255

STi0-7

Application Circuit with 6802 Processor

Fig. 10 shows an example of a complete circuit

which may be used to evaluate the chip.

For convenience, a 4 MHz crystal oscillator has been

used rather than a 4.096 MHz clock, as both are

within the limits of the chip’s specifications. The RC

delay used

with the

393 counters

ensures a

sufficient hold time for the FP signal, but the values

used may have to be changed if faster 393 counters

become available.

The chip is shown as memory mapped into the

MEK6802D3

system.

Chip

addresses

00-3F

correspond

to

processor

addresses

2000-203F.

Delay through the address decoder requires the

VMA signal to be used twice to remove glitches. The

MEK6802D3 board uses a 10K

Ω pullup on the MR

pin, which would have to be incorporated into the

circuit if the board was replaced by a processor.

Figure 9 - Four 8980s Arranged in a Non-Blocking 16 x 16 Configuration

IN 0/7

IN 8/15

8980

#1

STi0/7 STo0/7

8980

#2

STi0/7 STo0/7

8980

#3

STi0/7 STo0/7

8980

#4

STi0/7 STo0/7

OUT 0/7

OUT 8/15