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MT8982AS Datasheet(PDF) 4 Page - Mitel Networks Corporation |
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MT8982AS Datasheet(HTML) 4 Page - Mitel Networks Corporation |
4 / 19 page MT8982 ISO-CMOS 2-34 When an output channel is in message mode, the data for the output channel originates from the microcontroller. The microcontroller writes data to the Connect Memory location which corresponds to the output link and channel number. The contents of the Connect Memory are transferred directly to the serial-to-parallel converter one channel time before it is to be output. The Connect Memory data is output MSB first, repetitively once per frame, until it is changed by the microcontroller. If the output channel is configured in tristate mode, the TDM serial stream output will be placed in high impedance during that channel time. This mode is entered by configuring the channel into connection mode and then setting the tristate control bit. All channels on both output TDM streams can be tristated by pulling pin 16 (ODE) low. This overrides the individual channel programming. The Data and Connect Memories are dynamic memories. They are refreshed by the sequential addressing generated by C4i. Microcontroller Interface The MT8982 is controlled via a synchronous, serial microport. The microport is compatible with Intel's MCS-51 serial port Mode 0 specifications, Motorola's Serial Peripheral Interface (SPI) specifications, and National's MicroWire specifications. The port consists of a transmit data line (TxD), a receive data line (RxD), a chip select line (CS), and a synchronous clock input (SCLK). All memory locations and control functions on the MiniDX are accessed through this port. The microport may also be configured in serial bus mode where data is clocked into the Connect Memory in the same way as STi0 and STi1 are clocked into Data Memory. In serial microport mode, CS must be low to enable a microport access. SCLK clocks the serial microport data in or out through RxD and TxD, LSB first. The TxD output driver is tristated when it is inactive. This allows RxD and TxD to be connected together for a single TxD/RxD line as used in the INTEL MCS-51 microcontrollers. Figure 3 shows a serial microport access cycle. A microport access cycle (microcycle) begins with a falling edge on CS. Eight bits of data are clocked into RxD by the rising edge of SCLK. Two of these eight bits indicate whether the microcycle operation is a read or a write, the rest of the bits are used for addressing. These eight bits are defined as the command/ address byte (Table 1). If the microcyle operation is a write, another eight bits are clocked Figure 3 - Serial Microport Timing D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 RxD TxD SCLK CS Minimum delay between accesses equals 3.0 µsec. The Mini Dx: - latches received data in on the rising edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted. Subsequent byte is always data. Subsequent write microcycles may flow without raising CS. CS must go high after a read microcycle. COMMAND/ADDRESS DATA INPUT/OUTPUT COMMAND/ADDRESS - outputs transmit data on the falling edge of SCLK |
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