NCP81044DR2G datasheet(6/16 Pages) ONSEMI

Part #	NCP81044DR2G

Description	Low Voltage Synchronous Buck Controller

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NCP81044

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DETAILED OPERATING DESCRIPTION

General

The NCP81044 is a PWM controller intended for DC−DC

conversion from 5.0 V & 12 V buses. The devices have a 1

A internal gate driver circuit designed to drive N−channel

MOSFETs in a synchronous−rectifier buck topology. The

output voltage of the converter can be precisely regulated

down to 800 mV

±1.0% when the VFB pin is tied to VOUT.

The switching frequency, is internally set to 275 kHz. A high

gain operational transconductance error amplifier (OTA) is

used.

Duty Cycle and Maximum Pulse Width Limits

In steady state DC operation, the duty cycle will stabilize

at an operating point defined by the ratio of the input to the

output voltage. The devices can achieve an 80% duty cycle.

There is a built in off−time which ensures that the bootstrap

supply is charged every cycle. This part can allow a 12 V to

0.8 V conversion at 275 kHz.

Input Voltage Range (VCC and BST)

The input voltage range for both VCC and BST is 4.5 V to

13.2 V with respect to GND and PHASE, respectively.

Although BST is rated at 13.2 V with respect to PHASE, it

can also tolerate 26.4 V with respect to GND.

External Enable/Disable

When the Comp pin voltage falls or is pulled externally

below the 400 mV threshold, it disables the PWM Logic and

the gate drive outputs. In this disabled mode, the operational

transconductance amplifier (EOTA) output source current is

reduced and limited to the Soft−Start mode of 10

mA.

Normal Shutdown Behavior

Normal shutdown occurs when the IC stops switching

because the input supply reaches UVLO threshold. In this

case, switching stops, the internal SS is discharged, and all

GATE pins go low. The switch node enters a high impedance

state and the output capacitors discharge through the load

with no ringing on the output voltage.

External Soft−Start

The NCP81044 features an external soft−start function,

which reduces inrush current and overshoot of the output

voltage. Soft−start is achieved by using the internal current

source of 10

mA (typ), which charges the external integrator

capacitor of the transconductance amplifier. Figure 8 is a

typical soft−start sequence. This sequence begins once VCC

surpasses its UVLO threshold and OCP programming is

complete. During soft−start, as the Comp Pin rises through

400 mV, the PWM Logic and gate drives are enabled. When

the feedback voltage crosses 800 mV, the EOTA will be

given control to switch to its higher regulation mode output

current of 120

mA.

Figure 8. Soft−Start Implementation

4.2 V

0.9 V

0.8 V

Comp

VCC

Vfb

BG

TG

Vout

NORMAL

SS

POR

UVLO

550 mV

50 mV

OCP

Program

ming

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NCP81044DR2G Datasheet(PDF) 6 Page - ON Semiconductor

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