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MT90210AL Datasheet(PDF) 6 Page - Mitel Networks Corporation |
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MT90210AL Datasheet(HTML) 6 Page - Mitel Networks Corporation |
6 / 27 page MT90210 Preliminary Information 2-150 how the data from the serial port is mapped into the external dual port memory. Figure 3 - Dual Port RAM Memory Map for Mode 1 Mode 2: When the device is configured for 4.096 Mb/s data rate operation, each of the 24 time- division multiplexed serial streams is made up of 64 channels. In this data rate operation, the 24 serial lines (S0-23) become bidirectional links at 4.096 Mb/s. Serial port clock (SCLK) is 8.192 MHz. The on-chip PLL produces a phase locked 32.768 MHz clock (CKout) from the SCLK input. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Mode 3: When the device is configured for 8.192 Mb/s data rate operation, each of the 24 time- division multiplexed serial streams is made up of 128 channels. In this mode, bidirectional operation on the serial port streams is not provided and the MT90210 is set in a 12 in / 12 out configuration and the OEser input is ignored. Streams S0-S11 are configured as inputs, and S12-S23 are configured as outputs. Serial port clock is 16.384 MHz. The on-chip PLL doubles this clock to produce a CKout clock of 32.768 MHz. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Figure 12 and Table 3 show the write and read operations on the parallel port at the frame boundary. Figure 4 - Dual Port RAM Memory Map for Modes 2 and 3 Mode 4: The MT90210 is configured such that the 24 serial streams are bidirectional and split into two different functional groups: (i) streams S0-S15 operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23 operate at 8.192 Mb/s rate (1024 timeslots). Memory mapping for mode 4 is described in Figure 5. For compatibility with legacy MVIP timing, mode 4 provides an additional clock input at 4.096 MHz (HC4 input pin) which allows the device to detect frame sync pulse (F0i) with a typical width of 244 ns. In mode 4, the 16.384 (SCLK) and 4.096 (HC4) MHz clocks should be in sync according to H-MVIP specifications. The on-chip PLL doubles SCLK to produce a CKout signal of 32.768 MHz. Figure 13 and Table 4 show the write and read operations on the parallel port at the frame boundary. Mode 5: Identical operation as per mode 4 with the difference that the 16.384 MHz clock is a differential signal received at the two input pins, C16+ and C16- of the MT90210 device. The differential clock is needed to eliminate distortion in the clock signal passing through a ribbon cable as per H-MVIP specification. The SCLK input is not used in this mode. Memory mapping for mode 5 is depicted in Figure 5. 0000 0800 0FFF BLOCK 0 BLOCK 1 MODE 1 24 bidirectional streams at 2.048Mb/s Address outputs used: A0-A11; 768 bytes for TX 768 bytes for RX unused memory space Legend: 02FF 06FF 0AFF 0EFF 0400 0C00 768 bytes for TX 768 bytes for RX A12 always zero. 0000 1000 1FFF BLOCK 0 BLOCK 1 MODES 2 & 3 24 bidirectional streams at 4.096Mb/s, Address outputs used: A0-A12 1536 bytes for TX 1536 bytes for RX unused memory space or 12 in / 12 out at 8.192Mb/s Legend: 05FF 0DFF 15FF 1DFF 0800 1800 1536 bytes for TX 1536 bytes for RX |
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