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MT9079AC Datasheet(PDF) 11 Page - Mitel Networks Corporation |
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MT9079AC Datasheet(HTML) 11 Page - Mitel Networks Corporation |
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11 / 54 page  MT9079 4-247 TAIS Operation The TAIS (Transmit AIS) pin allows the PRI interface to transmit an all ones signal form the point of power-up without writing to any control registers. After the interface has been initialized normal operation can take place by making TAIS high. National Bit Buffers Table 4 shows the contents of the transmit and receive Frame Alignment Signals (FAS) and Non-frame Alignment Signals (NFAS) of time slot zero of a PCM 30 signal. Even numbered frames (CRC Frame # 0, 2, 4, ...) are FASs and odd numbered frames (CRC Frame # 1, 3, 5, ...) are NFASs. The bits of each channel are numbered 1 to 8, with 1 being the most significant and 8 the least significant. Table 4 - FAS and NFAS Structure Table 5 illustrates the organization of the MT9079 transmit and receive national bit buffers. Each row is an addressable byte of the MT9079 national bit buffer, and each column contains the national bits of an odd numbered frame of each CRC-4 Multiframe. The transmit and receive national bit buffers are selectible in microprocessor or microcontroller CRC CRC Frame/ Type PCM 30 Channel Zero 12345678 0/FAS C1 0011011 1/NFAS 01 ALM Sa4 Sa5 Sa6 Sa7 Sa8 2/FAS C2 0011011 3/NFAS 01 ALM Sa4 Sa5 Sa6 Sa7 Sa8 4/FAS C3 0011011 5/NFAS 11 ALM Sa4 Sa5 Sa6 Sa7 Sa8 6/FAS C4 0011011 7/NFAS 01 ALM Sa4 Sa5 Sa6 Sa7 Sa8 8/FAS C1 0011011 9/NFAS 11 ALM Sa4 Sa5 Sa6 Sa7 Sa8 10/FAS C2 0011011 11/NFAS 11 ALM Sa4 Sa5 Sa6 Sa7 Sa8 12/FAS C3 0011011 13/NFAS E1 1 ALM Sa4 Sa5 Sa6 Sa7 Sa8 14/FAS C4 0011011 15/NFAS E2 1 ALM Sa4 Sa5 Sa6 Sa7 Sa8 indicates position of CRC-4 multiframe alignment signal. modes, but cannot be accessed in ST-BUS mode. In ST-BUS mode access to the national bits can be achieved through the Transmit and Receive Non-frame Alignment Signal (CSTi0 and CSTo). When selected, the Data Link (DL) pin functions override the transmit national bit buffer function. The CALN (CRC-4 Alignment) status bit and maskable interrupt CALNI indicate the beginning of every received CRC-4 multiframe. Table 5 - MT9079 National Bit Buffers Note: NBB0 - NBB4 are addressable bytes of the MT9079 transmit and receive national bit buffers. Data Link Operation The MT9079 has a user defined 4 kbit/sec. data link for the transport of maintenance and performance monitoring information across the PCM 30 link. This channel functions using one of the national bits (Sa4, Sa5, Sa6, Sa7 or Sa8) of the PCM 30 channel zero non-frame alignment signal. The Sa bit used for the DL is selected by making one of the bits, Sa4 - Sa8, high in the Data Link Select Word. Access to the DL is provided by pins DLCLK, TxDL and RxDL, which allow easy interfacing to an HDLC controller. The 4 kHz DLCLK output signal is derived from the ST-BUS clocks and is aligned with the receive data link output RxDL. The DLCLK will not change phase with a received frame slip, but the RxDL data has a 50% chance of being lost or repeated when a slip occurs. The TxDL input signal is clocked into the MT9079 by the rising edge of an internal 4 kHz clock (e.g., internal data link clock IDCLK). The IDCLK is 180 degrees out of phase with the DLCLK. See Figures 20 and 21 for timing requirements. Addre ssable Bytes Frames 1, 3, 5, 7, 9, 11, 13 & 15 of a CRC-4 Multiframe F1 F3 F5 F7 F9 F11 F13 F15 NBB0 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 NBB1 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 NBB2 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 NBB3 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 NBB4 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 |
Similar Part No. - MT9079AC |
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Similar Description - MT9079AC |
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