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MT90810AK Datasheet(PDF) 7 Page - Mitel Networks Corporation |
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MT90810AK Datasheet(HTML) 7 Page - Mitel Networks Corporation |
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7 / 34 page  Preliminary Information MT90810 2-151 Figure 4 - Clock Control Functional Block Diagram SEC8K EX_8KA EX_8KB C4b X1 F0b Digital PLL 16MHz div 4 div 2 XCLK_SEL 0 1 2 PLL_MODE 1, 5 2, 6 3, 7 PLL_MODE X2 Jittery 4.096MHz 60ns peak jitter (sampler) Phase Comparator VCO External 8kHz div 4 8kHz 0 4 up/ PLL_LO PLL_LI external loop filter down External 16MHz Crystal SEC8K EX_8KA EX_8KB FRAME EN_SEC8K SEL_S8K 0 1 2 CLK8 C4b CLK4 C2o CLK2 FRAME F0b div by 2 @32MHz 16MHz 4.096MHz Analog PLL FMIC state machine 8kHz clock. The digital PLL state machine is clocked at 16.384MHz. The digital PLL maintains lock by occasionally dropping or repeating a 16.384MHz clock period on the generated 4.096MHz clock. Consequently, the 4.096MHz clock has jitter equal to about 60ns. If the output of the digital PLL is chosen as the input to the analog PLL, a slow loop filter with a time constant greater than several 8kHz frames will smooth out the jitter. The clock oscillator pins X1 and X2 can be used with an external 16.384MHz crystal or pin X1 can be used directly as a clock input with X2 left unconnected. When X1 is used as a clock input, the frequency of the clock can be selected to be either 16.384MHz or 8.192MHz or 4.096MHz by changing the XCLK_SEL bits in the CLK_CNTL register. The overall FMIC state machine from which all timing is derived, is clocked by the 16.384MHz output of the analog PLL, the device’s master clock. The state machine controls all timing in the FMIC and has a period equal to one MVIP frame (8kHz). This state machine can either free run or synchronize to an 8kHz source such as the MVIP F0 signal or an external 8kHz reference. Refer to Figure 4 - “Clock Control Functional Block Diagram” for further details. The operation of the PLLs and the state machine is controlled by the clock control register as described in Figure 6 - “Clock Control (CLK_CNTRL) Register” and Tables 8 to 10. The clock circuitry (PLLs and state machine) operates in eight different modes. They are: FMIC as Timing Master (Mode 0) The FMIC is configured as the timing master (CLK_CNTRL register cleared, PLL mode 0 selected) after reset. The external 16.384MHz input is divided by four and used as the input to the analog PLL so the internal master clock is phase locked to the 16.384MHz oscillator. The FMIC state machine is free-running and does not synchronize to any external 8kHz source. In this mode, the XLCK_SEL bits of the clock control register can be programmed to accommodate an 8.192MHz or 4.096MHz external clock instead of the default 16.384MHz. The FMIC becomes MVIP master when MVIP_MST bit is set in the Control/Status register. This mode can be used when the FMIC chip is to become timing master in a system which has no digital network connections (T1 or E1). FMIC as MVIP Slave (Mode 4) When this mode is selected, MVIP C4 clock is selected as the input to the analog PLL. The FMIC internal master clock is then synchronized to the MVIP bus timing. The FMIC state machine is also synchronized to the MVIP F0 framing signal. The MVIP_MST bit in the Control/Status register should never be set when the device is in mode 4 as the FMIC is entirely slave to the MVIP bus timing. |
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