MT91L62

Advance Information

7-174

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

13

Connect 0.1

µ F capacitor to V

14

Connect 0.1

µ F capacitor to V

15

PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).

16

IC

17

A/

µ

A/

µ Law Selection. CMOS level compatable input pin governs the companding law used by the

18

RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatable input.

19

TXMute

Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatable input.

20

21

22

CSL0

CSL1

CSL2

Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the

conversion rate between the externally supplied MCL clock and the 512 KHz clock required by a

filter/codec. Refer to Table 2 for details. CMOS level compatable input.

23

Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1

device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot

defined by STB.

24

Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the

falling edge of BCL during the timeslot defined by STB. CMOS level compatable input.

13

STB

Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and

receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable

input.

14

CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions.

Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin

when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input.

15

Positive Power Supply. Nominally 3 volts.

16

AOUT-

Inverting Analog Output. (balanced).

17

AOUT+

Non-Inverting Analog Output. (balanced).

18

Ground. Nominally 0 volts.

19

Ain-

Inverting Analog Input. No external anti-aliasing is required.

20

Ain+

Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.

AIN-

AIN+

VBias

VRef

IC

RXMute

CSL0

CSL1

CSL2

Din

Dout

VSS

AOUT +

AOUT -

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

PWRST

TXMute

STB

CLOCKin

A/

µ

20 PIN PDIP/SOIC/SSOP