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SP8861 Datasheet(PDF) 5 Page - Mitel Networks Corporation |
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SP8861 Datasheet(HTML) 5 Page - Mitel Networks Corporation |
5 / 13 page 5 SP8861 DESCRIPTION Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8861, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has counted by the pre-loaded number of cycles. While the A counter is counting, the dual modulus prescaler is held in the N11 mode then reverts to the N mode at the completion of the sequence. The M counter is a 15-bit asynchronous divider which counts with a ratio set by a control word. In both A and M counters the controlling data from the F1/F2 buffer is loaded in sequence with every M count cycle. The N ratio of the dual modulus prescaler is selected by a one-bit word in the reference divider buffer and, when when a ratio of 48/9 is selected, the A counter requires only three programming bits, having an impact on the frequency bit allocation as described in the data entry section. Reference Source and Divider The reference source in the SP8861 is obtained from an on-chip oscillator which is frequency controlled by an external crystal. The oscillator can also function as a buffer amplifier to allow the use of an external reference source. In this mode, the source is simply AC-coupled into the oscillator transistor base on pin 20. The oscillator output is coupled to a programmable reference counter ( R) whose output is the reference for the phase detector. The reference divider is a fully programmable 13-bit asynchronous design and can be set to any division ratio between 1 and 8191. The actual division ratio is controlled by a data word stored in the internal reference buffer. Phase Detector The SP8861 contains a digital phase detector which feeds two charge pump circuits. Charge pump 1 has preset currents which are programmble as shown in Table 1. Charge pump 2 has a current level set by an external resistor RPD; the current is multiplied by a factor which is determined by bits G1 and G2 of the F1 or F2 word (see Table 1). Note that charge pump 2 current is pin 24 current 3 muliplication factor, where I pin 24 = A lock detect circuit is connected to the output of charge pump 2. when the voltage level at pin 25 is between approximately 2·25V and 2·75V, LOCK DETECT (pin 27) will be low and charge pump 1 disabled, depending on the PD1 and PD2 programming bits as shown in Table 4. The output signals from the R and M counters are available on pins 4 and 5 (FPD and FREF) when programmed by the reference programming word; the various options are shown in Table 4. An external phase detector may be connected to pins 4 and 5 and may be used independently or in conjunction with the on-chip phase detector. To allow for control direction changes introduced by the design of the control loop, a control bit in the F1/F2 programming word interchanges the inputs to the on-chip phase detector and reverses the functions on pins 4 and 5 (see Table 2). VCC21·5V RPD F1 or F2 word G2 G1 Charge pump 1 current ( µA) Charge pump 2 multiplier 0 1 Current source Current sink FPD FREF F1/F2 sense bit Pins 3 and 25 Pin 4 Output for RF phase lag FREF FPD Pin 5 0 1 0 1 0 0 1 1 50 75 125 200 1 1·5 2·5 4 Table 1 Charge pump currents Table 2 Data Entry and Storage The data section of the SP8861 consists of a data input interface, a data shift register and three data buffers. Data is entered to the data input interface via a three-wire highway, with DATA (pin 24), CLOCK (pin 15) and ENABLE (pin16) inputs. The input interface routes the data into a 24- bit shift register with bus connections to three data buffers. Data entered via the serial bus is transferred to the appropriate data buffer on the negative transition of the data enable input according to the two final data bits C1 and C2 as shown in Table 3. The MSB of the data is entered first. 2-bit SR contents C2 C1 0 1 0 1 F1 F2 Transfer A counter bits (N0:N3) into 4-bit buffer (see Figs. 2 and 7) Reference 0 0 1 1 Buffer loaded Table 3 The dual F1/F2 buffer can receive two 22-bit words and controls the programmable divider A and M counters using 19 bits, the phase detector gain with two bits and the phase detector sense with one bit. A fourth input from the synthesiser control system selects the active buffer. The third buffer contains only 16 bits, 13 being used to set the reference divider division ratio and 2 to control the phase detector enable logic. The remaining bit sets the dual modulus prescaler N ratio. The data words may be entered in any individual multiple sequence and the shift register can be updated whils the data buffers retain control of the synthesiser with the previously loaded data. This enables four unique data words to be stored in the device, with three in the data buffers and a fourth in the shift register, while the chip is enabled. The F1 word may also be updated while F2 is controlling the programmable divider and vice-versa. The dual F1/F2 buffer enables allows the device to be toggled between two frequencies using the F1/F2 select input at a rate determined by the comparison frequency and also permits random frequency hopping at a rate determined by a btye load period; this is possible because the loop can be locked to F1 while F2 is updated by entering new data via the shift register. The F1/F2 input is high to select F1. |
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