VP16256

Programmable FIR Filter

Advance Information

The VP16256 contains sixteen multiplier - accumulators, which

can be multi cycled to provide from 16 to 128 stages of digital filtering.

Input data and coefficients are both represented by 16-bit two’s

complement numbers with coefficients converted internally to 12 bits

and the results being accumulated up to 32 bits.

In 16-tap mode the device samples data at the system clock rate

of up to 40MHz. If a lower sample rate is acceptable then the number

of stages can be increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the sample clock rate

must be halved with respect to the system clock. With 128 stages the

sample clock is therefore one eighth of the system clock.

In all speed modes devices can be cascaded to provide filters of

anylength,onlylimitedbythepossibilityofaccumulatoroverflow.The

32-bit results are passed between cascaded devices without any

intermediate scaling and subsequent loss of precision.

The device can be configured as either one long filter or two

separate filters with half the number of taps in each. Both networks

can have independent inputs and outputs.

Both single and cascaded devices can be operated in decimate-

by-two mode. The output rate is then half the input rate, but twice the

number of stages are possible at a given sample rate. A single device

witha40MHzclockwouldthen,forexample,providea128-stagelow

pass filter, with a 10MHz input rate and 5MHz output rate.

Coefficients are stored internally and can be down loaded from

a host system or an EPROM. The latter requires no additional

support, and is used in stand alone applications. A full set of

coefficientsisthenautomaticallyloadedatpoweron,orattherequest

of the system. A single EPROM can be used to provide coefficients

for up to 16 devices.

PIN 1 IDENT

PIN

208

PIN 1

GH208

Pin identification diagram (top view)

See Table 1 for pin descriptions and Table 2 for pinout

Fig. 2 Typical system application

FEATURES

Sample Rates

Sampling Rates Proportionally Reducing to 5MHz

Length Filters

Length

EPROM

ORDERING INFORMATION

VP16256-27/CG/GH1N 27MHz,

Commercial

plastic

PowerQuad PQ2 package (GH208)

VP16256-40/CG/GH1N 40MHz,

Commercial

plastic

PowerQuad PQ2 package (GH208)

APPLICATIONS

Supersedes August 1997 version, DS4548 - 3.2

DS4548 - 4.0 August 1998

Fig. 1 A dual filter application

ADDR DATA

EPROM

EPROM

GND

SCLK

RES

CHANGE

COEFF

POWER-ON

RESET

VP

16256

OUTPUT

DATA

INPUT

DATA

ADDR DATA

EPROM

GND

SCLK

RES

CHANGE

COEFF

POWER-ON

RESET

VP

16256

OUTPUT

DATA

ADC

COEFFICIENTS

EPROM

CLKOP

ANALOG

INPUT