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VP16256-27 Datasheet(PDF) 10 Page - Mitel Networks Corporation |
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VP16256-27 Datasheet(HTML) 10 Page - Mitel Networks Corporation |
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10 / 20 page  10 VP16256 (a) Single Filters 32 31 0 127 NOT USED 0 127 64 63 NOT USED 0 127 32 31 64 63 16 TAP 32 TAP 64 TAP NO SWAP POSSIBLE 0 127 128 TAP 16 15 LOWER BANK UPPER BANK LOWER BANK UPPER BANK LOWER BANK UPPER BANK (b) Dual Filters B UPPER BANK 32 31 0 127 NOT USED 32 31 0 127 64 63 96 95 NOT USED 48 47 0 127 16 15 32 31 64 63 8 TAP 16 TAP 32 TAP FILTER B NO SWAP POSSIBLE FILTER A NO SWAP POSSIBLE 0 127 64 63 64 TAP A LOWER B LOWER A UPPER B UPPER A UPPER BANK B LOWER BANK A LOWER BANK A LOWER B LOWER A UPPER B UPPER Fig. 13 Coefficient memory map FILTER CONTROL Two control modes are available selected by input signal FRUN. In EPROM load mode, when FRUN is tied high the device will commence operation once the coefficients have been loaded. The CLKOP signal indicates when new input data is required and that new results are available, see Fig. 6. In both EPROM and remote master load modes, when FRUN is tied low filter operation will not commence until a high has been detected on signal FEN. This mode allows synchronisation to an existing data stream. FEN should be taken high when the first valid data sample is available so that both are read into the device on the next SCLK rising edge.Proper device operation requires FEN to be low during control register and coefficient loading both in EPROM mode and Remote Master mode. After loading coefficients, filter operation is determined by FRUN and FEN as described above. During device reset RES must be held low for a minimum of 16 SCLK cycles. After a reset the control register returns to its default state of 8C80 HEX. This places the device into the following mode : q Single filter q Sample rate equal to the clock rate q Non-decimating q A single device (Not in a cascade chain) q Bank swap selected by bit in the control register COEFFICIENT BANK SWAP A Bank Swap feature is provided which allows all coefficients to be simultaneously replaced with a different set. A bit in the Control Register (CR7) allows the swap to be controlled by either input signal SWAP or Control Register bit (CR6). The latter is useful if the device is controlled by a microprocessor, when driving a separate pin would entail additional address decoding logic and an external latch. If SWAP or bit CR6 is low, the coefficients used will be those loaded into the lower banks illustrated in Fig. 13. When the SWAP or CR6 is high, the upper banks are used. The actual swap will occur when the next sampling clock active going transition occurs. This can be up to seven system clocks later than the swap transition, and is filter length dependent. The first valid filtered output will then occur after the pipeline latencies given in Tables 3 and 4. By setting a bit in the Control Register it is possible to bank |
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Similar Description - VP16256-27 |
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