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VP306 Datasheet(PDF) 9 Page - Mitel Networks Corporation |
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VP306 Datasheet(HTML) 9 Page - Mitel Networks Corporation |
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9 / 85 page  DRAFT - PRELIMINARY DATA VP305/6 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 9 VCO LPF LPF SL1710 I/Q DOWN CONVERT VP216/7 DUAL ADC IIN QIN SYS_CLK VCO LOOP FILTER LOOP FILTER 479.5MHz PSCAL CR_VCO SYM_VCO VP305/6 14.984375MHz AGC LOOP FILTER SAW SP5658 FREQ SYNTH. FROM LNB MICROPROCESSOR AGC_OUT /32 Fig. 2. System Application Diagram. 1.2. The QPSK Demodulator block. The QPSK demodulator block performs the function of locking the receiver system to the incoming data stream. It controls the voltage controlled oscillators (VCO) in the SL1710 I/Q down converter and the VP216/7 dual analog to digital converter (ADC). The carrier frequency VCO is locked to maintain the intermediate frequency (IF) of 479.5MHz. The symbol frequency VCO synthesiser loop is locked to the twice the required symbol frequency (in the zero decimation case) and generates the system clock SYS_CLK which is running at the bit rate. /32 VCO LPF LPF SYM_RP SL1710 I/Q DOWN CONVERT VP216/7 DUAL ADC IIN QIN SYS_CLK XTI VCO LOOP FILTER LOOP FILTER 479.5MHz PSCAL CR_VCO SYM_VCO VP305/6 14.984375MHz CR_RP SYM_NF AFC CR_U/LSWL CONV CONV VCO SWEEP GEN Fig. 3. Carrier and Symbol frequency synthesiser diagram. |
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Similar Description - VP306 |
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