VP306 datasheet(4/85 Pages) MITEL

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VP306 Datasheet(PDF) 4 Page - Mitel Networks Corporation

Part #	VP306

Description	Satellite Channel Decoder

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Manufacturer	MITEL [Mitel Networks Corporation]

Direct Link	http://www.mitel.com

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VP305/6

DRAFT - PRELIMINARY DATA

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

2.11.6. GPP_CTRL: General Purpose Port control register. .........................................54

2.11.7. RESET: Reset register. .....................................................................................55

2.12. BANK 7: Program test registers. ...................................................................................56

2.12.1. TEST1: Test 1 register - for diagnostic / qualification purposes only. ...............56

2.12.2. TEST2: Test 2 register - for diagnostic / qualification purposes only. ...............56

2.12.3. TEST3: Test 3 register - for diagnostic / qualification purposes only. ...............57

MICROPROCESSOR CONTROL. .........................................................................................58

3.1. I²C bus Interface............................................................................................................58

3.1.1. Examples of I²C bus messages: ........................................................................59

3.2. Parallel interface. ..........................................................................................................60

3.2.1. Examples of writing to and reading from the parallel interface. ..........................60

3.2.2. Parallel interface Write cycle description. ...........................................................60

3.2.3. Parallel interface Read cycle description. ...........................................................63

TIMING INFORMATION. ........................................................................................................65

4.1. I²C bus timing. ...............................................................................................................65

4.2. Parallel interface Write cycle timing. .............................................................................66

4.3. Parallel interface Read cycle timing. .............................................................................66

4.4. Data input timing. ..........................................................................................................67

MPEG PACKET DATA OUTPUT...........................................................................................68

5.1. Data output format.........................................................................................................68

5.2. Data output timing. ........................................................................................................ 70

VP305/6 OPERATING CONDITIONS. ...................................................................................71

6.1. Recommended operating conditions.............................................................................71

6.2. Electrical characteristics................................................................................................72

6.3. Crystal specification. ..................................................................................................... 73

6.4. Absolute maximum ratings. ...........................................................................................73

6.5. Pinout description..........................................................................................................74

6.6. Alphabetical listing of the pinout....................................................................................77

6.7. Numerical listing of the pinout. ......................................................................................78

REFERENCES. ......................................................................................................................80

APPENDIX 1: FEATURES .....................................................................................................81

APPENDIX 2: LOCK ACQUISITION ALGORITHM. ...............................................................82

9.1. Pre conditions. ..............................................................................................................82

9.2. Lock acquisition algorithm.............................................................................................82

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