VP520S

4

When it receives a REQYUV response from the next

system component, it starts to output a macroblock by using

an output strobe derived by dividing down the clock input.

Detailed timing is given in Figure 3. This strobe only occurs

when data is available at the output pins and at a rate of

SYSCLK/4. The 'Request Macroblock' flag must go inactive

and then active again before a further macroblock is made

available.

The Frame Ready flag is only available on the output pin

if the Frame Enable Bit is set in Control Register 1. Through

this control bit a host controller is able to determine whether a

new frame is to be compressed and transmitted. In an alterna-

tive arrangement the control bit can be permanently set, and

the Frame Ready Flag is then used as an interrupt to the host

controller. It then generates a signal which is used as the

Frame Ready signal for the next device.

The following sections describe this interface as it applies

to the VP2611 H261 Video Encoder.

TRANSFERING MACROBLOCKS TO THE VP2611

When the VP520S has stored a complete field of deci-

mated video in the DRAM, it raises a Frame Ready Flag ( FSIG

). If the bit in Control Register 1 does not inhibit the output, this

flag becomes the FRMIN input on the VP2611. This responds

to the FRMIN input by generating a Request for Macroblock

Data ( REQYUV ). The VP2611 MUST then receive a com-

plete macroblock ( 384 bytes ) within 1870 cycles of the

system clock. When the VP520S is producing decimated CIF/

QCIF data, writing line data to the DRAM has priority, and only

four macroblock read operations are possible in every 32

clock cycles i.e. one read takes eight cycles. These, however,

are 16 bit word operations and it thus requires 384 x 8/2 = 1536

cycles to output the data. In addition there is a maximum delay

of 60 clock periods from receiving REQYUV to producing the

first output strobe (MCLK). This is still well within the time

available.

The four 16 bit words are stored in the VP520S and

transmitted to the VP2611 as eight bytes using a strobe

( MCLK ) derived from the system clock. This is only present

when valid data is available, and it drives the PCLK input on

the VP2611.

It takes the VP2611 almost exactly all the available time at

30 Hz frame rates to process all the macroblocks. After a field

time ( half an interlaced frame ) the VP520S will start to write

new data to the DRAM, and data could be overwritten during

the last macroblocks. Since there is available space in the

DRAM, a small address offset is used between video fields to

avoid this problem.

INTERPOLATE MODE

In this mode the VP520S expects to receive CIF/QCIF

data in macroblock format, which it then writes to an external

frame store. This is then read back in line format and passed

through vertical and horizontal interpolating filters to produce

two fields of CCIR601 video. Detailed input timing is given in

Figure 4.

FSIG automatically becomes an input which is used to

identify the start of a frame and to reset the internal address

counter. FSIG must stay high until a complete CIF/QCIF frame

has been received ( internal logic counts macroblocks ). If

FSIG goes low early then the complete frame will be ignored,

and the previously received frame will continue to be dis-

played.

An input strobe, derived by dividing the system clock by

four, must also be provided in order to input data. This must

only be present when valid data is available on the input pins.

Incoming macroblocks are byte wide, and these are internally

buffered to allow four 16 bit words to be written to the DRAM

every 32 system clock cycles. This is equivalent to a byte input

rate of SCLK/4 which must not be exceeded.

The CIF frame store is double buffered such that a new

frame can be received whilst the previous one is being

displayed. In fact the use of 256K x 16 DRAM's gives sufficient

capacity for more than three complete CIF frames, and the

internal address generator will simply roll around to make full

use of the available space.

Once a complete CIF/QCIF frame has been received, it will

normally be used to generate two interlaced PAL or NTSC

fields. These fields continue to be re-generated until a com-

plete new CIF frame has been received. The rate of receiving

frames depends on the transmission bandwidth, but the

maximum rate is 30 Hz. The changeover to the newly received

frame will occur when the VP520S has finished generating

any one of the pair of interlaced fields for display, it does not

First Cr Component Valid

First O/P Valid

HBLANK

O/P

INPUT

CLOCK

LUM

OUTPUT

CREF

O/P

20ns

max

Second O/P Valid

CHROM

O/P

First Cb

Valid

20ns max

20ns

max

20ns max

20ns max

20ns max

20ns max

33ns min

MCLK

I/P

FSIG

I/P

Second I/P

First I/P

40ns min

40ns min

4SCLK min

10ns min 2ns min

DATA

I/P

Fig 4 : Macroblock Input Timing

Fig 5 : Luminance and Chrominance Output Timing

Table 1. External DRAM Timing Requirements

t RAC

Access time from RAS

-

105ns or under

t CAC

Access time from CAS

-

25ns or under

t RP

RAS precharge time

50ns or under

-

t CP

CAS precharge time

12ns or under

-

t RAS

RAS pulse width

80ns or under

-

t CAS

CAS pulse width

50ns or under

-

t REF

Time between

complete refreshes

-

4 ms or over

(8 ms with 256k x n)

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

N.B. All times are quoted assuming 27MHz operation. For lower clock

frequencies increase the above values proportionately.