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WL102

Advance Information

WL102 System Overview

The WL102 is a highly integrated digital wireless

transceiver controller suitable for controlling multiple

channel radios with data rates up to 1Mbit/s 2-level data or

2Mbit/s 4-level data. It has been designed to interface easily

with the WL600 and WL800 radio transceiver chips.

The use of low power synchronous on chip RAM and

selective power down of system blocks makes the WL102

ideally suited to power sensitive applications. Also the

WL102 can be operated from 3V or 5V supply rails with level

translation between the Host and MAC system built in to the

Host Interface. A minimum configuration of the WL102 with

a 64Kbyte external ROM for code storage makes it ideal for

small footprint applications, and the option of 100 pin or 144

pin TQFP 1mm packages make it suitable for PC-Card

applications.

The 100 pin package option allow the WL102 to be used in

the lowest cost solution. This includes all the internal blocks

of the WL102 hardware plus the option of an external

processor, to replace the internal 8051 core, and the

external system RAM and / or other peripherals on the

processor bus. The 144 pin package includes the 100 pin

features plus the option of using an external data buffer

RAM (up to 64K), to replace the internal 6.4K buffer RAM,

and the option of using the parallel synthesiser load pins the

are active in DE6003 mode of the CCB block, the Datasheet

DS4837 should be checked for further information on this

option.

It is envisaged that the WL102 hardware will allow the

development of a wireless network to the Media Access

Layer of the IEEE model for networking, with the addition

of an LLC layer providing the equivalent of the Data Link

layer of the ISO network model. In such a system the Host

interface buffer RAM would provide the boundary between

the LLC layer running on the Host and the MAC layer on the

internal WL102 8051 processor, or an optional external

MAC system processor.

Figure 1 shows the internal architecture of the WL102.

The WL102 provides an interface between a Host system,

such as a PC or PDA, which can be a PC-Card interface or

an 8 bit microprocessor bus, and an interface designed for

use with the DE6038 (WL600/WL800) radio transceiver.

The host interface provides a buffer and interrupt signalling

mechanisms between the Host and Mac system

processors. The MAC system processor is required to

provide the timing and control functions of Media Access

Control.

The Communications Control Block performs transmit and

receive operations directly to the buffer RAM so minimising

the load on the MAC system processor. A minimum

controller system configuration would be the WL102 plus

an external code memory device.

WL102 Hardware Blocks

System Processor

The WL102 contains an embedded processor, identical in

operation to an industry standard 8051 microcontroller,

with the exception that the internal data memory is

increased from 128 to 256 bytes.

System busses and strobes allow the 8051 to access the

full 64 Kbytes of external code memory. Internal

connections exist to the processor's two interrupt inputs,

and to the two timer inputs. Two I/O port pins are internally

connected to blocks within the WL102, whilst four of the

remaining I/O port pins are brought out to external pins,

including the serial receive and transmit port pins. Internal

address decoding provides access to the other blocks of

the device, with 36 Kbytes of the processor's 64 Kbytes

address range being unassigned and available for the

addition of external peripheral devices.

The 8051 demultiplexed address and data bus are

available externally to allow for the addition of extra

memory or other peripheral devices.

The 8051 is clocked at the internal system clock frequency

of 10MHz.

If additional processing power is required for a particular

application the WL102 may also be used with an external

processor instead of the internal 8051. This external

processor also accesses the WL102 blocks via the internal

address decode. Interrupt and Counter outputs are

brought to external pins and two control signals must also

be provided to the WL102.

Data RAM

The WL102 contains 4 Kbytes of static RAM which the

processor may use for variable storage etc. If additional

storage space is required, an external static RAM may also

be used, and mapped to an unused area of the WL102

memory map.