TLC7226C, TLC7226I, TLC7226M

QUADRUPLE 8BIT DIGITALTOANALOG CONVERTERS

SLAS060F − JANUARY 1995 − REVISED APRIL 2009

8

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

AGND bias for positive output offset (continued)

_

+

DAC A

AGND

DGND

TLC7226†

Vref

OUTA

4

18

2

6

3

VDD

5

VSS

VI

Vbias

† Digital inputs omitted for clarity.

Figure 5. AGND Bias Circuit

interface logic information

Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of

the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the

selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the

addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value

corresponding to the data held in their respective latches.

Table 2. Function Table

CONTROL INPUTS

OPERATION

WR

A1

A0

OPERATION

H

L

↑

L

↑

L

↑

L

↑

X

L

L

L

L

H

H

H

H

X

L

L

H

H

L

L

H

H

No operation

Device not selected

DAC A transparent

DAC A latched

DAC B transparent

DAC B latched

DAC C transparent

DAC C latched

DAC D transparent

DAC D latched

L = low,

H = high,

X = irrelevant