SMBCLK

P

S

SMBDAT

P

S

LM95235

LM95235-Q1

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SNIS142F – APRIL 2006 – REVISED MARCH 2013

SMBus Digital Switching Characteristics (continued)

The switching characteristics of the LM95235 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95235. They

adhere to, but are not necessarily, the SMBus specifications.

Parameter

Test Conditions

Typical

Limits

Unit

(1)

(2)

(Limit)

Output Fall Time

250

ns (max)

(4)

SMBDAT and SMBCLK Time Low for

25

ms (min)

35

ms (max)

Data In Setup Time to SMBCLK High

250

ns (min)

300

ns (min)

Data Out Stable after SMBCLK Low

1075

ns (max)

Start Condition SMBDAT Low to

SMBCLK Low (Start condition hold

100

ns (min)

before the first clock falling edge)

Stop Condition SMBCLK High to

100

ns (min)

SMBDAT Low (Stop Condition Setup)

SMBus Repeated Start-Condition Setup

0.6

µs (min)

Time, SMBCLK High to SMBDAT Low

SMBus Free Time Between Stop and

1.3

µs (min)

Start Conditions

(5)

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

Figure 2. SMBus Communication

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